A semiconductor package includes a package substrate, an interposer on the package substrate, a lower molding layer on the package substrate and surrounding the interposer, a first semiconductor chip on the lower molding layer, a chip connection terminal between the first semiconductor chip and the package substrate and surrounded by the lower molding layer, a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip, interposer connection terminals that connect the first and second semiconductor chips to the interposer, and an upper molding layer on the lower molding layer and surrounding the first and second semiconductor chips.

A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.

A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.