H01L23/13

Stacked die cavity package

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Stacked die cavity package

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Assortment of substrates for semiconductor circuits, corresponding assortment of devices and method

A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.

Assortment of substrates for semiconductor circuits, corresponding assortment of devices and method

A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

MODULE AND METHOD FOR MANUFACTURING SAME
20230013032 · 2023-01-19 ·

A module includes a substrate having a first surface and at least one recess on the first surface, and an electronic component mounted on the first surface. The electronic component is connected to the substrate via a plurality of bumps. All of the plurality of bumps are connected to the first surface inside any of the at least one recess. A height of the plurality of bumps is greater than a depth of the at least one recess. When viewed in a direction perpendicular to the first surface, a part of the electronic component is located outside an outer periphery of any recess selected from the at least one recess.

Fabric With Embedded Electrical Components

Electrical components may have plastic packages. Contacts may be formed on exterior surfaces of the plastic packages. A plastic package for an electrical component may have an elongated shape that extends along a longitudinal axis. A first groove may run parallel to the longitudinal axis on a lower surface of the plastic package. A second groove may run perpendicular to the first groove on an opposing upper surface of the plastic package. The electrical components may be coupled to fibers in a fabric such as a woven fabric. A first solder connection may be formed between the first groove and a first fiber such as a weft fiber. A second solder connection may be formed between the second groove and a second fiber such as a warp fiber.

Fabric With Embedded Electrical Components

Electrical components may have plastic packages. Contacts may be formed on exterior surfaces of the plastic packages. A plastic package for an electrical component may have an elongated shape that extends along a longitudinal axis. A first groove may run parallel to the longitudinal axis on a lower surface of the plastic package. A second groove may run perpendicular to the first groove on an opposing upper surface of the plastic package. The electrical components may be coupled to fibers in a fabric such as a woven fabric. A first solder connection may be formed between the first groove and a first fiber such as a weft fiber. A second solder connection may be formed between the second groove and a second fiber such as a warp fiber.

PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGES
20230223387 · 2023-07-13 ·

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.