A method of manufacturing a metal structure for an optical semiconductor device, including a treatment step (1) of immersing in and/or applying the solution containing a polyallylamine polymer a base body, the base body including an outermost layer at a portion or entire surfaces of the base body, the outermost layer including a plating of at least one selected from the group consisting of gold, silver, a gold alloy, and a silver alloy, so as to manufacture the metal structure for an optical semiconductor device having an increased adhesion to a resin material.

A ceramic circuit substrate having high bonding performance and excellent thermal cycling resistance properties, wherein a ceramic substrate and a copper plate are bonded by a braze material containing Ag and Cu, at least one active metal component selected from Ti and Zr, and at least one element selected from among In, Zn, Cd, and Sn, wherein a braze material layer, after bonding, has a continuity ratio of 80% or higher and a Vickers hardness of 60 to 85 Hv.

A circuit board that has flexibility owing to an organic insulating layer and that still has high adhesion between metal wiring and the organic insulating layer; and a method for producing the circuit board without employing photolithography. The circuit board comprising a metal wiring arrangement portion and a metal wiring non-arrangement portion, wherein: in the metal wiring arrangement portion, metal wiring, a first diffusion layer, and a first organic insulating layer are stacked; in the metal wiring non-arrangement portion, a metal oxide layer, a second diffusion layer, and a second organic insulating layer are stacked; the metal wiring is made of a first metal element; and the first diffusion layer contains the first metal element and a second metal element.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

The present disclosure provides a semiconductor package capable of improving performance and reliability. The semiconductor package of the present disclosure includes a first device and a second device that are electrically connected to each other, the first device includes a substrate, a first pad formed on an upper side of the substrate, and a passivation film formed on the upper side of the substrate and formed to surround the first pad, the second device includes a second pad placed to face the first pad, and the first pad has a center pad having a first elastic modulus and an edge pad having a second elastic modulus smaller than the first elastic modulus, the edge pad formed to surround the center pad and to contact the passivation film.

The present disclosure provides a semiconductor package capable of improving performance and reliability. The semiconductor package of the present disclosure includes a first device and a second device that are electrically connected to each other, the first device includes a substrate, a first pad formed on an upper side of the substrate, and a passivation film formed on the upper side of the substrate and formed to surround the first pad, the second device includes a second pad placed to face the first pad, and the first pad has a center pad having a first elastic modulus and an edge pad having a second elastic modulus smaller than the first elastic modulus, the edge pad formed to surround the center pad and to contact the passivation film.

An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.

Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.