A method of forming a self-aligned waveguide is provided. The method includes providing a radio frequency (RF) interposer. The RF interposer includes a non-conductive substrate, a radiating element formed on the non-conductive substrate, and a cavity formed in the non-conductive substrate. A packaged semiconductor die is affixed in the cavity of the RF interposer. A conductive material is dispensed to form a conductive path between a conductive connector of the packaged semiconductor die and the radiating element.

A method of forming a self-aligned waveguide is provided. The method includes providing a radio frequency (RF) interposer. The RF interposer includes a non-conductive substrate, a radiating element formed on the non-conductive substrate, and a cavity formed in the non-conductive substrate. A packaged semiconductor die is affixed in the cavity of the RF interposer. A conductive material is dispensed to form a conductive path between a conductive connector of the packaged semiconductor die and the radiating element.

In a semiconductor-mounting heat dissipation base plate including: an insulating substrate to which a metal circuit layer for mounting a semiconductor chip thereon is fixed; a heat dissipation base formed from the same metal material as the metal circuit layer at a side opposite to the metal circuit layer across the insulating substrate and fixed to the insulating substrate similar to the metal circuit layer; and a strengthening member provided in the heat dissipation base so as to be separated from the insulating substrate, the sizes of crystal grains of a metal structure at a part of the heat dissipation base or the metal circuit layer are reduced by a crystal size reducing material adhered to a mold, thereby preventing an adverse effect of a columnar crystal structure.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.

A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

An integrated circuit comprises a substrate including a shape memory polymer, and a semiconductor die mounted on the substrate.

Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.