A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

An apparatus is shown and described herein that is suitable for supporting a substrate in a process chamber or other application and providing a desired thermal leveling profile. The apparatus is configured to provide a thermal leveler that is detachable from the apparatus.

Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.

A semiconductor structure and a method for forming a semiconductor structure are disclosed. A form of a method for forming a semiconductor structure includes: providing a base; patterning the base, to form a substrate and fins protruding out of the substrate, where each fin includes a bottom fin and a top fin located on the bottom fin, and in a direction perpendicular to an extension direction of each fin, a width of the top fin is less than a width of the bottom fin; and forming an isolation structure on the substrate exposed by a fin, where the isolation structure covers at least a sidewall of the bottom fin, and a top of the isolation structure is lower than a top of the fin. In the present disclosure, a bottom fin with a larger width is formed, to increase the volume of the bottom fin, and the area of a contact surface of the fin and the substrate, and to correspondingly enhance an effect of dissipating heat generated during working of a device to the substrate, thereby improving the heat dissipation performance of the device, and to correspondingly improving a self-heating effect of the device, so that the device performance is further improved.

A CMOS-based sensing device includes a substrate including an etched portion and a first region located on the substrate. The first region includes a membrane region formed over an area of the etched portion of the substrate, a flow sensor formed within the membrane region and a pressure sensor formed within the membrane region.

A thermal conductive member includes: first and second surface layers including an insulating material A, and an intermediate layer including an insulating material B. The insulating material A includes a first boron nitride sintered body having an orientation degree of hexagonal boron nitride primary particles of 0.6 to 1.4, and a first heat curable resin composition impregnating in the first boron nitride sintered body. The insulating material B includes a second boron nitride sintered body having an orientation degree of hexagonal boron nitride primary particles of 0.01 to 0.05, and a second heat curable resin composition impregnating in the second boron nitride sintered body.

A heater includes a base body, a resistance heating element, and a terminal part. The base body is made of ceramic and is plate shaped including an upper surface on which a wafer is superimposed and a lower surface on an opposite side to the upper surface. The resistance heating element is located inside the base body. The terminal part is electrically connected to the resistance heating element, is at least partially located inside the base body, and is exposed from, the lower surface of the base body to an exterior of the base body. The lower surface of the base body includes an adjacent region which surrounds the terminal part. The adjacent region includes an inclined surface in a portion reaching the terminal part.

Novel integrated circuit environmental and temperature sensors in combination with measurement circuitry fully integrated as part of an ASIC die, which may be co-packaged with a pressure sensor integrated circuit to create a compact yet sensitive environment monitoring product. Embodiments may include one or more integrated local heating elements and control circuitry that are power supply independent, make efficient use of battery power, include an accurate in-built temperature detection capability, and provide digital close-loop control of the heating elements.

A micro heater chip, a wafer-level electronic chip assembly and a chip assembly stacking system are provided. The chip assembly stacking system includes a plurality of wafer-level electronic chip assemblies stacked on top of one another and electrically connected with each other. Each wafer-level electronic chip assembly includes a wafer-level electronic chip and a micro heater chip disposed on the wafer-level electronic chip. The micro heater chip includes a heating structure and an insulative structure disposed between the heating structure and the wafer-level electronic chip. The heating structure includes a carrier body, at least one micro heater disposed on or inside the carrier body, and a plurality of conductive connection layers passing through the carrier body. The insulative structure includes an insulative body disposed between the heating structure and the wafer-level electronic chip, and a plurality of conductive material layers passing through the insulative body.

Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.