Patent classifications
H01L23/345
INTEGRATED HEAT SPREADER (IHS) WITH HEATING ELEMENT
Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.
Sensing device, sensing apparatus and sensing system
A sensing device includes a first III-V compound stack and a second III-V compound stack. The first III-V compound stack has a first sensing area, and the second III-V compound stack has a second sensing area. A passivation layer fully covers the second sensing area. The first III-V compound stack is physically separated from the second III-V compound stack, and has material compositions and structures same as the second III-V compound stack.
PACKAGE HEATERS FOR COLD TEMPERATURE OPERATION AND METHOD
A semiconductor package comprises two or more dies including at least one integrated circuit. The package can further include a heater element. The heater element can be configured to radiate heat, within one or more of a metal layer and a diffusion layer of at least one of the two or more dies of the semiconductor package. The package can further include controller interface configured to receive a heater enablement signal to initiate or terminate operation of the heater element. Other systems, apparatuses and methods are described.
ELECTRONIC-COMPONENT-MOUNTED MODULE
An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/ C.
Low cycle fatigue prevention
A system for reducing low cycle fatigue of a soldered connection includes a controller and a heating element operatively connected to the controller. The system also includes a printed wire board soldered in connection with an electronic component. The controller is configured to retrieve a signal indicative of a temperature of the electronic component, and compare the temperature to a stored predetermined range of operating temperatures. Responsive to determining that the temperature of the electronic component is less than a lower threshold temperature of the predetermined range of operating temperatures, the controller transmits a signal to the heating element that causes the heating element to heat the electronic component. The controller then saves, to an operatively connected computer readable memory, a magnitude of temperature difference and a number of times that magnitude is reached. The controller uses the stored information to track the life of the electronic component.
Transistor implemented heat source
A heat source comprised of one or more transistors or transistor packages mechanically connected to a heat plate. The heat generation is accomplished by the direct and precisely controlled heat generated by one or more transistors through the precise duty cycle control of a high-frequency Pulse-Width-Modulated (PWM) which is generated based on the sensed temperature and current generated by one or more of the transistor(s).
Top-side connector interface for processor packaging
An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.
Image sensor package having multi-level stack structure
An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.
Apparatus having a cavity structure and method for producing same
The present disclosure relates to an apparatus having a substrate arrangement with a first circuit arrangement that heats up during operation and a second circuit arrangement that is integrated into a substrate material of the substrate arrangement. Further, the apparatus has a cavity structure that is arranged between the first and the second circuit arrangement, said cavity structure being formed in the substrate material and having a pressure that is lower than an ambient atmospheric pressure.
METHOD FOR MANUFACTURING AN ELECTRICALLY OPERABLE HEATING BODY FOR AN INHALER
Method for manufacturing an electrically operable heating body for an inhaler, wherein a semiconductor material is provided so as to be substantially planar, and a plurality of channels are incorporated into the semiconductor material substantially in the direction of the surface normal of the planar semiconductor material, such that a fluid can pass through the semiconductor material in the channels.