A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.

An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

A biosensor with a heater embedded therein is provided. A semiconductor substrate comprises a source region and a drain region. The heater is under the semiconductor substrate. A sensing well is over the semiconductor substrate, laterally between the source region and the drain region. A sensing layer lines the sensing well. A method for manufacturing the biosensor is also provided.

Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

One or more heating elements are provided to heat a MEMS component (such as a resonator) to a temperature higher than an ambient temperature range in which the MEMS component is intended to operate—in effect, heating the MEMS component and optionally related circuitry to a steady-state “oven” temperature above that which would occur naturally during component operation and thereby avoiding temperature-dependent performance variance/instability (frequency, voltage, propagation delay, etc.). In a number of embodiments, an IC package is implemented with distinct temperature-isolated and temperature-interfaced regions, the former bearing or housing the MEMS component and subject to heating (i.e., to oven temperature) by the one or more heating elements while the latter is provided with (e.g., disposed adjacent) one or more heat dissipation paths to discharge heat generated by transistor circuitry (i.e., expel heat from the integrated circuit package).

Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

A test wafer according to an embodiment of the present disclosure is a test wafer used for simulation of heat emission of devices on a wafer, and includes a silicon wafer and a silicon heater bonded to a surface of the silicon wafer.

An integrated circuit having a body comprised of semiconducting material has one or more electronic components formed in a first region of the body and at least another electronic component formed in the second region of the body. A thermal barrier separates the two regions. By one approach that thermal barrier comprises a gap formed in the body. The gap may comprise an air gap or may be partially or wholly filled with material that inhibits thermal conduction. The thermal barrier may at least substantially surround the aforementioned second region. The second region may also include one or more temperature sensors disposed therein. A temperature control circuit may use the corresponding temperature information from within the second region to actively control the second region temperature using a temperature forcing element that is disposed at least proximal to the second region.

An optical waveguide for optical signals is formed in a semiconductor layer of an SOI substrate, a heater for heating the optical waveguide is formed on a silicon oxide film which covers the optical waveguide, and wirings for supplying power to the heater are connected to both ends of the heater. Each of the wirings is constituted of a laminated film of a bottom barrier metal film, an aluminum-copper alloy film serving as a main conductive film and a top barrier metal film, and the heater is constituted integrally with the bottom barrier metal film constituting a part of each of the wirings.