Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.

A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

On-chip peltier cooling devices and manufacturing methods thereof are provided. The device comprises: a first type well, a polysilicon gate and dummy gates, first type doped regions, a second type doped region, a first and second via. The dummy gate is formed as a two-segment structure with an interval, and there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate. The first type doped region at least overlaps with an orthographic projection region of the first segment of the dummy gate on the semiconductor substrate. The second type doped region at least overlaps with orthographic projection regions of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate. In this application, the heat flows from inside of the device to its surface, to realize heat dissipation and cooling.

On-chip peltier cooling devices and manufacturing methods thereof are provided. The device comprises: a first type well, a polysilicon gate and dummy gates, first type doped regions, a second type doped region, a first and second via. The dummy gate is formed as a two-segment structure with an interval, and there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate. The first type doped region at least overlaps with an orthographic projection region of the first segment of the dummy gate on the semiconductor substrate. The second type doped region at least overlaps with orthographic projection regions of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate. In this application, the heat flows from inside of the device to its surface, to realize heat dissipation and cooling.

Integrated cooling device based on Peltier effect and manufacturing method thereof are provided. The device comprises one or more first heat dissipation structures around a device area. Each first heat dissipation structure comprises first N-type deep doped regions and first P-type deep doped regions arranged alternately, first vias, and first metal interconnection layers. The first vias are respectively located on two ends of each first N-type and each first P-type deep doped region. The first metal interconnect layers connect the first vias and such that the first heat dissipation structures are connected as a first S-shaped structure. When the first S-shaped structure is turned on, heat in the first N-type deep doped regions and the first P-type deep doped regions flows from a side close to the device area to its other side away from the device area, so as to realize heat dissipation in the device area.

Integrated cooling device based on Peltier effect and manufacturing method thereof are provided. The device comprises one or more first heat dissipation structures around a device area. Each first heat dissipation structure comprises first N-type deep doped regions and first P-type deep doped regions arranged alternately, first vias, and first metal interconnection layers. The first vias are respectively located on two ends of each first N-type and each first P-type deep doped region. The first metal interconnect layers connect the first vias and such that the first heat dissipation structures are connected as a first S-shaped structure. When the first S-shaped structure is turned on, heat in the first N-type deep doped regions and the first P-type deep doped regions flows from a side close to the device area to its other side away from the device area, so as to realize heat dissipation in the device area.

A sensor device according to the present disclosure includes a Peltier element, a sensor element thermally connected to a cooling surface of the Peltier element, and a window member that faces a light receiving surface of the sensor element and is made of borosilicate glass.