Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material, in which a width of an upper end of the upper conductive material is greater than a width of the corresponding upper conductive material.

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.