A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.

A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.

A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.

A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.

An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.

An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.

A chip for controlled electrostatic discharging to avoid loading on input/output pins, comprising: a die comprising: a first plurality of connector pins each conductively coupled to one or more signal paths, each of the first plurality of connector pins having a first height; and a second plurality of connector pins independent of any signal paths, each of the second plurality of connector pins having a second height greater than the first height.

A chip for controlled electrostatic discharging to avoid loading on input/output pins, comprising: a die comprising: a first plurality of connector pins each conductively coupled to one or more signal paths, each of the first plurality of connector pins having a first height; and a second plurality of connector pins independent of any signal paths, each of the second plurality of connector pins having a second height greater than the first height.

A semiconductor device including a first structure including a first dielectric layer and a first conductive pattern in the first dielectric layer, the first conductive pattern including a first conductive material and a first bonding enhancement material; a second structure including a second dielectric layer and a second conductive pattern in the second dielectric layer, the second dielectric layer directly contacting the first dielectric layer, the second conductive pattern directly contacting the first conductive pattern; and a first bonding enhancement layer between the first conductive pattern and the second dielectric layer, wherein the first bonding enhancement layer includes the first bonding enhancement material or a material of the second dielectric layer, and the first bonding enhancement material includes a material having a higher bonding force to the material of the second dielectric layer than a bonding force of the first conductive material to the material of the second dielectric layer.

A semiconductor device including a first structure including a first dielectric layer and a first conductive pattern in the first dielectric layer, the first conductive pattern including a first conductive material and a first bonding enhancement material; a second structure including a second dielectric layer and a second conductive pattern in the second dielectric layer, the second dielectric layer directly contacting the first dielectric layer, the second conductive pattern directly contacting the first conductive pattern; and a first bonding enhancement layer between the first conductive pattern and the second dielectric layer, wherein the first bonding enhancement layer includes the first bonding enhancement material or a material of the second dielectric layer, and the first bonding enhancement material includes a material having a higher bonding force to the material of the second dielectric layer than a bonding force of the first conductive material to the material of the second dielectric layer.