A semiconductor device according to an embodiment includes a substrate, an -ray shielding layer, a first semiconductor chip, and a second semiconductor chip. The -ray shielding layer is provided on the substrate. The first semiconductor chip is provided on the -ray shielding layer. The second semiconductor chip is provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.

A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.

A semiconductor memory includes a substrate having a first surface, a memory device mounted on the first surface, a controller mounted on the first surface, and a shielding layer between the first surface and at least a part of the controller, the shielding layer having a thickness that is large enough to block most of the alpha radiation from the substrate from reaching the part of the controller.

A semiconductor memory includes a substrate having a first surface, a memory device mounted on the first surface, a controller mounted on the first surface, and a shielding layer between the first surface and at least a part of the controller, the shielding layer having a thickness that is large enough to block most of the alpha radiation from the substrate from reaching the part of the controller.

A semiconductor device according to an embodiment includes a substrate, an -ray shielding layer, a first semiconductor chip, and a second semiconductor chip. The -ray shielding layer is provided on the substrate. The first semiconductor chip is provided on the -ray shielding layer. The second semiconductor chip is provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

A semiconductor device according to an embodiment includes a substrate, an -ray shielding layer, a first semiconductor chip, and a second semiconductor chip. The -ray shielding layer is provided on the substrate. The first semiconductor chip is provided on the -ray shielding layer. The second semiconductor chip is provided on the first semiconductor chip, whose operation is controlled by the first semiconductor chip.

A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.

A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.

In a semiconductor device, a first interposer has a first main surface. A second interposer is disposed on the first main surface. The second interposer has a second main surface on a side opposite to the first interposer. A material of the second interposer is different from that of the first interposer. A first semiconductor chip has a first front surface. The first semiconductor chip is mounted on the second main surface through a plurality of bump electrodes with the first front surface facing the second main surface. The first semiconductor chip includes a volatile memory circuit. A second semiconductor chip is mounted on a plurality of electrode patterns disposed on the first main surface or the second main surface through a plurality of bonding wires. The second interposer overlaps the first semiconductor chip in a direction perpendicular to the first main surface.