A mesh grid protection system is provided. The protection system includes a plurality of grid lines forming a mesh grid proximate to operational logic. The protection system also includes tamper-detection logic coupled to the plurality of grid lines and configured to toggle a polarity of a signal on at least one grid line at each clock cycle and to detect attempts to access the operational logic by comparing a reference signal driving a first end of a grid line to a signal at the opposite end of the grid line.

The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

An electronic chip and a method of making thereof is provided, where the electronic chip includes at least: an electronic circuit arranged at a front face of a substrate; a first protective layer arranged on a rear face of the substrate; a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit; a second protective layer covering at least the resistive element; and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

An integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard applications. In one embodiment, the integrated circuit comprises a silicon-on-insulator (SOI) structure, a radiation insensitive sub-circuit, and a radiation sensitive sub-circuit. The SOI structure comprises a silicon substrate, a buried oxide layer, and an active silicon layer. The radiation insensitive sub-circuit is formed on the active layer, and includes a partially depleted transistor. The radiation sensitive sub-circuit is formed on the active layer, and includes a fully depleted transistor, to prevent operation of the radiation sensitive sub-circuit under specified radiation conditions. Each of the partially depleted transistor and the fully depleted transistor includes a channel region formed in the active silicon layer, and the channel regions of the partially depleted transistor and the fully depleted transistor have substantially the same thickness but different doping concentrations.

A circuit board is protected by being enclosed in a security housing that includes conductive tamper traces running along its interior surface, the conductive tamper traces being a housing portion of a tamper detection circuit. The tamper detection circuit also includes a board portion that detect tampering with the tamper detection circuit by monitoring voltages at monitor nodes along the board portion. The board portion of the tamper detection circuit is connected to the tamper traces via multiple connector pieces. The connector pieces can be held in place by board connector piece holders affixed to the board or housing connector piece holders of the housing. When tampering is detected, it can be localized based on voltages measured at multiple recesses along the housing. The tamper detection circuit can be arranged in a wheatstone bridge layout for environmental tolerance. The circuit board's functions/components can be disabled if tampering is detected.

A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.

According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.

A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

Embodiments relate to the authentication of a semiconductor. An identification circuit disposed within a package of an integrated circuit, and the identification circuit includes carbon-nanotube transistors configured to generate an encryption key.

Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.