A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers of the three-dimensional integrated circuit. The input output circuit has first and second input output circuitry, wherein the first input output circuitry operates faster than the second input output circuitry.

A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers of the three-dimensional integrated circuit. The input output circuit has first and second input output circuitry, wherein the first input output circuitry operates faster than the second input output circuitry.

A wave phased array is manufactured using additive manufacturing technology (AMT). The wave phased array includes a radiator, a radiator dilation layer supporting the radiator, a beamformer supporting the radiator dilation layer, a beamformer dilation layer supporting the beamformer, and a substrate support layer supporting the beamformer dilation layer. At least one of the radiator, the radiator dilation layer, the beamformer, the beamformer dilation layer and the substrate support layer is fabricated at least in part by an AMT process.

Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.