Systems and methods for RF hazard protection are provided. In one embodiment, a RF protection coupler comprises: a first port to couple to an output of an RF source circuit; a second port to couple to an external RF load; a source side and load side RF switches, wherein the source side RF switch and the load side RF switch are each switch between a first and second states in response to a detected matting. In the first state the source and load side RF switches establish an electrical path between the first and second ports. In the second state: the source side RF switch couples the first port to an impedance load that is impedance matched to the output of the RF source circuit; the load side RF switch couples the second port to an electrical ground; and a gap between the switches electrically isolates the ports.

Systems and methods for RF hazard protection are provided. In one embodiment, a RF protection coupler comprises: a first port to couple to an output of an RF source circuit; a second port to couple to an external RF load; a source side and load side RF switches, wherein the source side RF switch and the load side RF switch are each switch between a first and second states in response to a detected matting. In the first state the source and load side RF switches establish an electrical path between the first and second ports. In the second state: the source side RF switch couples the first port to an impedance load that is impedance matched to the output of the RF source circuit; the load side RF switch couples the second port to an electrical ground; and a gap between the switches electrically isolates the ports.

In one embodiment, methods for making semiconductor devices are disclosed.

In one embodiment, methods for making semiconductor devices are disclosed.

A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

A symmetrical layout technique for an electrostatic discharge ESD device and a corresponding power supply network is presented. The ESD device protects an electronic circuit against an overvoltage or overcurrent and contains a first contact area to establish an electrical contact with a first supply rail, a second contact area to establish an electrical contact with a second supply rail, and a third contact area to establish an electrical contact with a third supply rail. The first and third supply rails provide a first supply voltage, and the second supply rail provides a second supply voltage. Within the ESD device, an axis of symmetry passes through the second contact area, and the first contact area and the third contact area are arranged on opposite sides with regard to the axis of symmetry. The symmetrical layout technique allows flipping the orientation of the ESD device with regard to the supply rails.

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.