Isolators for high frequency signals transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may include resonators capable of operating at high frequencies with high bandwidth, high transfer efficiency, high isolation rating, and a small substrate footprint. In some embodiments, the isolators may operate at a frequency not less than 30 GHz, not less than 60 GHz, or between 20 GHz and 200 GHz, including any value or range of values within such range. The isolators may include isolator components galvanically isolated from and capacitively coupled to each other. The sizes and shapes of the isolator components may be configured to control the values of equivalent inductances and capacitances of the isolators to facilitate resonance in operation. The isolators are compatible to different fabrication processes including, for example, micro-fabrication and PCB manufacture processes.

Coupling apparatuses, circuits having such coupling apparatuses and corresponding methods are provided that involve a first and a second signal being coupled out from an out-coupling circuit part and being separately coupled into first and second circuit pmts. The use of different coupling mechanisms effects signal separation in this case. In particular, one of the signals can be coupled as a differential signal and the other as a common mode signal.

A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.

A tuning structure to mitigate a capacitive discontinuity in an integrated circuit (IC) package includes an electrical conductor having a first end, a second end, and a conductor body between the first end and the second end. The first end is electrically coupled to a signal via, and the second end electrically coupled to an IC package core via cap. The electrical conductor is disposed substantially coplanar with the core via cap, and the conductor body is disposed along an outer perimeter of the core via cap. The second end is coupled to the via cap at a contact location. The contact location is determined based on a measurement of a performance metric associated with the transmission path through the IC package core, the core via cap, the electrical conductor, and the signal via.

A tuning structure to mitigate a capacitive discontinuity in an integrated circuit (IC) package includes an electrical conductor having a first end, a second end, and a conductor body between the first end and the second end. The first end is electrically coupled to a signal via, and the second end electrically coupled to an IC package core via cap. The electrical conductor is disposed substantially coplanar with the core via cap, and the conductor body is disposed along an outer perimeter of the core via cap. The second end is coupled to the via cap at a contact location. The contact location is determined based on a measurement of a performance metric associated with the transmission path through the IC package core, the core via cap, the electrical conductor, and the signal via.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

Isolators for signals and/or powers transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may have working voltages, for example, higher than 500 Vrms, higher than 1000 Vrms, or between 333 Vrms and 1800 Vrms. The isolators may have a fully symmetrical configuration. The isolators may include a primary winding coupled to a driver and a secondary winding coupled to a receiver. The primary and secondary windings may be laterally coupled to and galvanically isolated from each other. The primary and secondary windings may include concentric traces. The primary and secondary windings may be fabricated using a single metallization layer on a substrate.

According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.

Described examples include an apparatus including a package substrate having a die attach pad and a first semiconductor die on the die attach pad, the first semiconductor die including a transmitter. The apparatus also includes an assembly having a first plate coupled to the transmitter, a second plate separated from the first plate by a dielectric and a second semiconductor die on the die attach pad, the second semiconductor die including a receiver coupled to the second plate.

Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein. To that end, the bondwire inductor is fabricated by extending a bondwire connecting two connection pads of the semiconductor package around a dielectric structure, e.g., a dielectric post or posts, disposed between the connection pads a defined amount. In so doing, the bondwire inductor adds inductance between the connection pads, where the added inductance is defined by factors which at least include the amount the bondwire extends around the dielectric structure. Such additional inductance may be particularly beneficial for certain semiconductor devices and/or circuits, e.g., monolithic microwave integrated circuits (MMICs) to control or supplement impedance matching, harmonic termination, matching biasing, etc.