Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

A semiconductor device includes a semiconductor layer that includes a semiconductor substrate having a first thickness and has a main surface, a main surface electrode that is arranged at the main surface and has a second thickness less than the first thickness, and a pad electrode that is arranged on the main surface electrode and has a third thickness exceeding the first thickness.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

A method for tuning a resonant frequency of wireless communication circuitry on a multichip module including a plurality of chips includes applying an electrical insulator to an upper surface of the multichip module; creating a plurality of openings in the electrical insulator, each opening being positioned at a successive one of the bond pads to be electrically connected to create a plurality of exposed bond pads; applying metal to each exposed bond pad to form a successive one of a plurality of interconnect bases; removing a portion of the layer of photoresist to create a plurality of bridge supports, each bridge support positioned between a successive pair of interconnect bases; applying metal to each bridge support and associated interconnect bases to form a successive one of the interconnect traces; removing the bridge supports; and disconnecting one or more of the interconnect traces as necessary to obtain a target resonant frequency.

The present disclosure relates to a method for manufacturing electronic chips comprising, in order: a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed; b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate; c. forming first trenches of a first width on the side of a second face of the semiconductor substrate; d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate; e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.

A die stack includes: a first die including a first semiconductor substrate; a second die including a second semiconductor substrate; a bonding dielectric structure including a bonding polymer and that bonds the first die and the second die; a bonding interconnect structure that extends through the bonding dielectric structure to bond and electrically connect the first die and the second die; and a bonding dummy pattern that extends through the bonding dielectric structure to bond the first die and the second die. The bonding dummy pattern is electrically conductive and is electrically floated.

A package structure and a formation method of a package structure are provided. The method includes forming a recess in a circuit substrate, and the recess has a first sidewall and a second sidewall. The second sidewall is between the first sidewall and a bottommost surface of the circuit substrate, and the second sidewall is steeper than the first sidewall. The method also includes forming a die package, and the die package has a semiconductor die. The method further includes bonding the die package to the circuit substrate through bonding structures such that a portion of the semiconductor die enters the recess of the circuit substrate. In addition, the method includes forming an underfill material to surround the bonding structures and to fill the recess.

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

A semiconductor device includes a semiconductor element, a conducting member, a conductive bonding material, a resin member and a first barrier layer. The semiconductor element includes an element first surface and an element second surface facing away from each other in a thickness direction, with the element first surface provided with an electrode. The conducting member includes an obverse surface facing the element first surface and a reverse surface facing away from the obverse surface. The conductive bonding material is disposed between the electrode and the obverse surface of the conducting member. The resin member covers at least a portion of the conducting member, the semiconductor element and the conductive bonding material. The first barrier layer is disposed between the electrode and the conductive bonding material to prevent a reaction between the electrode and the conductive bonding material.

In an embodiment, an apparatus includes an energy source, a support platform for holding a wafer, an optical path extending from the energy source to the support platform, and a photomask aligned such that a patterned major surface of the photomask is parallel to the force of gravity, where the optical path passes through the photomask, where the patterned major surface of the photomask is perpendicular to a topmost surface of the support platform.