A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the present invention includes a first circuit body having a first semiconductor element and a first conductor portion, a second circuit body having a second semiconductor element and a second conductor portion, a resin sealing material for sealing the first circuit body and the second circuit body, and a warpage suppression portion that is formed along an array direction of the first circuit body and the second circuit body and is formed to have greater rigidity than a sealing portion of the resin sealing material, wherein the warpage suppression portion is formed of the same material as a resin member of the resin sealing material and is formed to be thicker than the sealing portion of the resin sealing material.

A semiconductor module includes a first power semiconductor element having a first surface and a second surface. The semiconductor module also includes a second power semiconductor element having a first surface and a second surface. The semiconductor module also includes first, second, third, and fourth conductor plates, and a connecting part. The connecting part is integrally formed with the second conductor plate, extends toward the third conductor plate, and is connected to the third conductor plate.

A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

A method for fabricating a hermetic electronic package includes providing a package body; hermetically coupling a package base plate to the package body; thermally coupling a substrate to the base plate; thermally mounting a semiconductor device to the substrate; bonding at least one high-current input/output (I/O) terminal to the first metalized region of the substrate by a strap terminal that is an integral high current heatsink terminal. A ceramic seal surrounding the at least one high-current I/O terminal is hermetically bonded to an outer surface of the package body. A metal hermetic seal washer surrounding the at least one high-current I/O terminal is hermetically bonded to the ceramic seal and to a portion of the at least one high-current I/O terminal. A lid is seam welded onto the package body.

A low-cost semiconductor package using a conductive metal structure includes a lead frame including a pad and a lead, a semiconductor chip attached onto the pad of the lead frame, an Aluminum (Al) pad formed on the semiconductor chip, a clip structure having one side adhered to the Al pad and the other side adhered to the lead of the lead frame, and a sealing member formed to surround the semiconductor chip and the clip structure via molding, wherein the semiconductor chip is adhered directly to a junction of the lead frame through a first adhesive layer formed of a solder or epoxy resin-based material and is adhered directly to a junction of the Al pad and the clip structure through a second adhesive layer formed of a solder-based material.

The semiconductor device includes: a heat spreader; a plurality of semiconductor elements; and one or a plurality of temperature detection elements. If a line segment connecting centers of two respective adjacent ones of the semiconductor elements is defined as X, a straight line that passes through one of the centers of the two adjacent semiconductor elements and that is perpendicular to X and parallel to the one-side surface of the heat spreader is defined as Y1, and a straight line that passes through another one of the centers of the two adjacent semiconductor elements and that is perpendicular to X and parallel to the one-side surface of the heat spreader is defined as Y2, at least a part of the temperature detection element is located in an arrangement region interposed between Y1 and Y2, as seen in a direction perpendicular to the one-side surface of the heat spreader.

A semiconductor package according to an embodiment of the present invention includes: a heat sink board including an insulated board and a first metal layer formed on the insulated board; at least one semiconductor chip placed on the first metal layer; a plurality of lead frames connected to the semiconductor chips used to electrically connect the semiconductor chips to the outside; and a package housing partially covering the heat sink board, wherein both end parts of the insulated board are projected further than both end parts of the first metal layer.

A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.