A power module is provided. The power module includes a substrate, and the substrate is used to carry components and pins of the power module. A circuit layer is disposed on the substrate, to complete an electrical connection between the carried components. The components and the pins are disposed on a same surface of the substrate, and the components and the pins are electrically connected by using the substrate. The power module further includes a sealing layer. The sealing layer is sleeved on the pins, the pins are partially exposed on a surface that is of the sealing layer and that faces away from a plastic packaging layer, and a space for accommodating the plastic packaging layer is formed between the sealing layer and the substrate.

A semiconductor device includes a first bus bar, a second bus bar, a first terminal, and a second terminal. The first terminal includes one or more planar portions, and the second terminal includes one or more planar portions. The one or more planar portions of the first terminal and the one or more planar portions of the second terminal are arranged parallel to and opposite each other. One of the first bus bar and the second bus bar covers a gap between a portion of the first terminal connected to the first bus bar and a portion of the second terminal connected to the second bus bar in plan view.

The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture. Some embodiments may include: depositing a base within an epitaxial layer; implanting a source implant extending into the base, wherein the epitaxial layer, the base, and the source implant form a continuous plane surface; depositing an insulating layer on the continuous plane surface forming a gate in contact with both the epitaxial layer and the base; opening a contact groove through the insulating layer to expose a central portion of the source implant; depositing a layer of photoresist on top of the insulating layer above exposed portions of the source implant; patterning a set of stripes in the photoresist, each stripe perpendicular to the contact groove; etching the set of stripes with an etch chemistry selective to the insulating layer; and filling the contact groove with a conductive material creating a base-source contact groove reaching through the insulating layer to the surface of the source implant and comprising a plurality of sections spaced apart from each other reaching through the source implant into the base.

A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

A semiconductor device includes a semiconductor body of a wide-bandgap semiconductor material. A plurality of first bond areas is connected to a first load terminal of the semiconductor device. First gate fingers are arranged between the first bond areas. The first gate fingers extend in a first lateral direction and branch off from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. A sum of the first length and the second length is equal to or greater than a lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.

A semiconductor device having an arm block. The arm block includes a first circuit pattern that, in a plan view of the semiconductor device, has a recess formed thereon that extends inward from a side thereof, the recess forming a disposition area of the semiconductor device, a second circuit pattern having at least a part disposed in the disposition area, and a plurality of semiconductor chips formed on the first circuit pattern. Each semiconductor chip has a positive electrode on a back surface thereof, and a control electrode and a negative electrode on a front surface thereof, the negative electrode being electrically connected to the second circuit pattern by a wiring member.

A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

A method for exposing a microwire from it glass coating in a glass coated microwire. The method for exposing the microwire is facilitated by way of sufficiently bending the glass coated microwire to break the glass coating while maintaining the embedded microwire intact.

The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.

A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.