A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through respective stoppers that provide a gap between the channel couplers and the interconnect channel. Each channel coupler can comprise a coplanar waveguide, a microstrip line, and a patch-antenna based coupler. The interconnect can enable communication between integrated circuits using signal waves having a frequency between 100 GHz and 3 THz.

Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.

An alignment system arranges a plurality of micro-elements at positions on a mounting substrate, the micro-elements are equal in dimension and shape. The alignment system encompasses a rough alignment-apparatus including a picker having capturing-probes, each of which having a capturing-face and a magnetic-force applying portion provided on the capturing-face, and a base-plate on which the capturing-probes are arrayed with an array-pattern. In the alignment system, each of the magnetic-force applying portions applies magnetic lines on the magnetic-force receptor to capture one of the micro-elements.