A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected. The source electrode of the MOSFET chip and the second external electrode are connected.

A double sided cooling module that includes a leadframe with a top Direct Copper Bonded (DCB) substrate and two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate, a spaced-apart row of first wires attached to a top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer, a semiconductor die having a bottom side load path contact attached to a top surface of a die pad portion of the top metal layer, a top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer, and an electrically conductive and thermally conductive spacer that is attached to the top side load path contact and to a bottom metal layer of the top DCB substrate. At least one of the first wires is attached to the control pad portion of the top metal layer and to a bottom metal layer of the top DCB substrate. Other ones of the first wires are attached to the die pad portion of the top metal layer and to the bottom metal layer of the top DCB substrate.

Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes additively forming and photocuring a 3D structure. The 3D structure is characterized by one or more three-dimensional flexible interconnects (3FIs), an upper level, a lower level, and a pedestal portion. The pedestal portion includes an undercut. The undercut defines an upper level overhang configured to define a mask region over a portion of the lower level. The method includes forming at least two electrically isolated planes of electronic circuitry by directionally depositing a selected material on the one or more 3FIs, the upper level, and one or more non-masked portions of the lower level.

A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function, and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.

A power electronic circuit device has a substrate, with multiple conductive tracks, and a power semiconductor component on these conductive tracks has a connection device with a metal sheet which electrically connects a contact pad of the power semiconductor component to a contact pad of a further power semiconductor component or a conductive track, and has a pressure device. The connection device includes a contact section for connection to an assigned contact pad and a connecting section arranged between the two contact sections. The pressure device includes a two-dimensional resilient pressure element that comprises pressure element sections, and first pressure element sections press with a first pressure surface section onto a contact section and second pressure element section presses with a second pressure surface section press onto the connecting section.

A light emitting module includes a light emitting device, a heat dissipating plate, and a holder. The light emitting device has a light extraction window and a plurality of electrodes. The light emitting device is secured to the heat dissipating plate. The heat dissipating plate is secured to the holder. The holder includes a plurality of terminals respectively connected to the electrodes of the light emitting device. The heat dissipating plate includes an exposed portion exposed from the holder when viewed from a side of the light emitting module on which the light extraction window of the light emitting device is provided.

The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components.

We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a semiconductor unit locator comprising a plurality of holes, wherein each semiconductor unit is located in each hole of the semiconductor unit locator; a plurality of pressure means for applying pressure to each semiconductor unit, and a conductive malleable layer located between the plurality of pressure means and the semiconductor unit locator.

A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.