According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.

An integrated circuit (IC) package, e.g., a power MOSFET package, may include a lead frame including (a) a main lead frame structure including a plurality of leads and defining or lying in a main lead frame plane, and (b) an offset lead frame die-attach pad (DAP) defining or lying in an offset plane that is offset from the main lead frame plane. The power IC package may further include a semiconductor die having a first side attached to the offset lead frame DAP, and a conductive element attached to both (a) a second side of the semiconductor die and (b) the main lead frame structure. The lead frame including the offset DAP may emulate the functionality of a copper clip, thus eliminating the need for the copper clip. The power IC package may also exhibit enhanced heat dissipation capabilities.

An object of the invention is to provide: a manufacturing method for a highly reliable power semiconductor device which prevents breakage of an conductor pattern and an insulating layer, and has bonding strength higher than that by the conventional bonding between the electrode terminal and the conductor pattern; and that power semiconductor device. Breakage of the conductor pattern and the insulating layer is prevented due to inclusion of: a step of laying an electrode terminal on a protrusion provided on a conductor pattern placed on a circuit-face side of a ceramic board so that a center portion of a surface to be bonded of the electrode terminal makes contact with a head portion of the protrusion; a step of pressurizing and ultrasonically vibrating a surface opposite to the surface to be bonded, of the electrode terminal, using an ultrasonic horn, to thereby bond the electrode terminal to the conductor pattern.

A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame structure defining a central clamp opening adapted to expose a portion of the leadframe strip. The frame structure includes at least one elongate frame member having a first surface portion adapted to engage a top surface of the leadframe strip and a second surface portion adapted to engage upper surfaces of integrated circuit (IC) component stacks mounted on the leadframe strip.

A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame structure defining a central clamp opening adapted to expose a portion of the leadframe strip. The frame structure includes at least one elongate frame member having a first surface portion adapted to engage a top surface of the leadframe strip and a second surface portion adapted to engage upper surfaces of integrated circuit (IC) component stacks mounted on the leadframe strip.

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

An apparatus includes a circuit substrate including a circuit trace and a micro-sized semiconductor device die electrically connected to the circuit substrate. The micro-sized semiconductor device die has a height not greater than 400 microns and a width not greater than 800 microns. An anisotropic conductive adhesive (ACA) is disposed between the circuit substrate and the micro-sized semiconductor device die, thereby providing an electrical connection from the circuit substrate to the micro-sized semiconductor device die.

A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame structure defining a central clamp opening adapted to expose a portion of the leadframe strip. The frame structure includes at least one elongate frame member having a first surface portion adapted to engage a top surface of the leadframe strip and a second surface portion adapted to engage upper surfaces of integrated circuit (IC) component stacks mounted on the leadframe strip.

The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100 C., preferably at most 60 C., advantageously at most 20 C. and ideally at most 5 C. and/or deviates from the operating temperature of the component by at most 50 C., preferably by at most 20 C., in particular by at most 10 C. and ideally by at most 5 C., preferably by at most 2 C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.