A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.

A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

The semiconductor device includes: a heat spreader; a semiconductor element joined to the heat spreader via a first joining member; a first lead frame joined to the heat spreader via a second joining member; a second lead frame joined to the semiconductor element via a third joining member; and a mold resin. In a cross-sectional shape obtained by cutting at a plane perpendicular to a one-side surface of the heat spreader, an angle on the third joining member side out of two angles formed by a one-side surface of the semiconductor element and a straight line connecting an end point of a joining surface between the third joining member and the semiconductor element and an end point of a joining surface between the third joining member and the second lead frame, is not smaller than 90° and not larger than 135°.

A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

A semiconductor package includes a semiconductor chip including a second bonding insulating layer surrounding at least a portion of each of a first bonding pad structure and a second bonding pad structure, in which the first bonding pad structure includes a first contact portion, a first bonding pad, and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, the second bonding pad structure includes a second contact portion, a second bonding pad, and a second seed layer disposed between the second bonding pad and the second contact portion and extending in the first direction, and the second bonding insulating layer is in contact with a side surface of each of the first and second seed layers and the first and second bonding pads.