A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A semiconductor device A1 disclosed includes: a semiconductor element 10 having an element obverse face and element reverse face that face oppositely in a thickness direction z, with an obverse-face electrode 11 (first electrode 111) and a reverse-face electrode 12 respectively formed on the element obverse face and the element reverse face; a conductive member 22A opposing the element reverse face and conductively bonded to the reverse-face electrode 12; a conductive member 22B spaced apart from the conductive member 22A and electrically connected to the obverse-face electrode 11; and a lead member 51 having a lead obverse face 51a facing in the same direction as the element obverse face and connecting the obverse-face electrode 11 and the conductive member 22B. The lead member 51, bonded to the obverse-face electrode 11 via a lead bonding layer 321, includes a protrusion 521 protruding in the thickness direction z from the lead obverse face 51a. The protrusion 521 overlaps with the obverse-face electrode 11 as viewed in the thickness direction z. This configuration suppresses deformation of the connecting member to be pressed during sintering treatment.

A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.

PROBLEM: To provide a multi-layer preform sheet capable of forming a highly reliable and high-quality electric interconnect, an electro-conductive bonding portion and so forth that are less likely to produce the Kirkendall void.

SOLUTION: A multi-layer preform sheet having at least a first layer and a second layer, the first layer being composed of a solder material that contains an intermetallic compound, and the second layer containing a first metal having a melting point of 300° C. or above, and a second metal capable of forming an intermetallic compound with the first metal.

A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.

Provided is a technique suitable for multilayering thin semiconductor elements via adhesive bonding while avoiding wafer damage in a method of manufacturing a semiconductor device, the method in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method of the present invention includes bonding and removing. In the bonding step, a back surface 1b side of a thinned wafer 1T in a reinforced wafer 1R having a laminated structure including a supporting substrate S, a temporary adhesive layer 2, and the thinned wafer 1T is bonded via an adhesive to an element forming surface 3a of a wafer 3. A temporary adhesive for forming the temporary adhesive layer 2 contains a polyvalent vinyl ether compound, a compound having two or more hydroxy groups or carboxy groups and thus capable of forming a polymer with the polyvalent vinyl ether compound, and a thermoplastic resin. The adhesive contains a polymerizable group-containing polyorganosilsesquioxane. In the removing step, a temporary adhesion by the temporary adhesive layer 2 between the supporting substrate S and the thinned wafer 1T is released to remove the supporting substrate S.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A semiconductor module includes a wiring substrate and two semiconductor devices mounted on the wiring substrate. The semiconductor module includes a housing having a rectangular frame body including four side walls. The housing includes a beam that bridges first side walls. A bus bar includes two end portions, upright portions each extending from one of the end portions in the thickness direction of an insulating substrate, bent portions each extending continuously with one of the upright portions, and an extension extending continuously with the bent portions. A section of the extension is embedded in the housing.