A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.

A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

Provided is a clip structure for a semiconductor package comprising: a first bonding unit bonded to a terminal part of an upper surface or a lower surface of a semiconductor device by using a conductive adhesive interposed therebetween, a main connecting unit which is extended and bent from the first bonding unit, a second bonding unit having an upper surface higher than the upper surface of the first bonding unit, an elastic unit elastically connected between the main connecting unit and one end of the second bonding unit, and a supporting unit bent and extended from the other end of the second bonding unit toward the main connecting unit, wherein the supporting unit is formed to incline at an angle of 1° through 179° from an extended surface of the main connecting unit and has an elastic structure so that push-stress applying to the semiconductor device while molding may be dispersed.

It is an object to provide technology enabling suppression of contact deformation of pin fins during assembly of a semiconductor device and the like. A semiconductor device includes a base plate, a semiconductor element, and a resin member. The base plate has a plurality of pin fins on a lower surface thereof. The semiconductor element is mounted on an upper side of the base plate. The resin member covers at least a side surface of the semiconductor element. The resin member has a rib covering a side surface of the base plate, and a lower end of the rib is located below lower ends of the plurality of pin fins.

A process for batch fabrication of circuit components is disclosed via simultaneously packaging multiple circuit component dice in a matrix. Each die has electrodes on its tops and bottom surfaces to be electrically connected to a corresponding electrical terminal of the circuit component it's packaged in. For each circuit component in the matrix, the process forms preparative electrical terminals on a copper substrate. Component dice are pick-and-placed onto the copper substrate with their bottom electrodes landing on corresponding preparative electrical terminal. Horizontal conductor plates are then placed horizontally on top of the circuit component dice, with bottom surface at one end of each plate landing on the dice's top electrode. An opening is formed at the opposite end and has vertical conductive surfaces. A vertical conductor block is placed into the opening and lands on the preparative electrical terminal, and the opening's vertical conductive surfaces facing the top end side surface of the vertical block. A thermal reflow then simultaneously melts pre-applied soldering material so that each circuit component die and its vertical conductor block are soldered to the copper substrate below and its horizontal conductor plate above.

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

A copper paste for joining contains metal particles and a dispersion medium, in which the copper paste for joining contains copper particles as the metal particles, and the copper paste for joining contains dihydroterpineol as the dispersion medium. A method for manufacturing a joined body is a method for manufacturing a joined body which includes a first member, a second member, and a joining portion that joins the first member and the second member, the method including: a first step of printing the above-described copper paste for joining to at least one joining surface of the first member and the second member to prepare a laminate having a laminate structure in which the first member, the copper paste for joining, and the second member are laminated in this order; and a second step of sintering the copper paste for joining of the laminate.

Provided is a semiconductor module, including: a semiconductor chip including a semiconductor substrate and a metal electrode provided above the semiconductor substrate; a protective film provided above the metal electrode; a plated layer provided above the metal electrode, having at least a part being in a height identical to the protective film; a solder layer provided above the plated layer; and a lead frame provided above the solder layer, wherein the plated layer is provided in a range not in contact with the protective film.

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.