A coupling element for providing external coupling to a semiconductor die within an integrated circuit package. The coupling element comprises a flexible laminate structure comprising a flexible, electrically insulating substrate layer, a first conductive layer bonded to a first surface of the substrate layer, and a second conductive layer bonded to a second surface of the substrate layer. The coupling element is arranged to be coupled to the semiconductor die such that the first and second conductive layers are electrically coupled to electrical contacts of the semiconductor die. The coupling element is further arranged to extend through the integrated circuit package when electrically coupled to the semiconductor die, and for the first and second conductive layers to be further electrically coupled to at least one external component.

The invention relates to a semiconductor component with a chip, especially with a high-frequency switching circuit. The semiconductor component further comprises a metal body on the chip and a supplementary circuit board. The supplementary circuit board is provided on an underside facing away from the metal body for connection with a printed-circuit board by means of reflow soldering.

A pressing ram having an elastic cushion element and intended for the material-bonded press-sintering connection of a first connection partner to a second connection partner of a power-electronics component. The elastic cushion element of the pressing ram is enclosed by a dimensionally stable frame, within which the cushion element and a guide part of the pressing ram are guided for linear movement such that the dimensionally stable frame lowers onto the first connection partner, or a workpiece carrier with the first connection partner arranged therein, and, following abutment against the same, the pressing ram together with the elastic cushion element is lowered onto the second connection partner and the elastic cushion exerts a pressure necessary for connecting the first connection partner to the second connection partner.

The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

A double-sided chip on film (COF) packaging structure and a manufacturing method thereof are disclosed. The double-sided COF structure includes a metal layer, a first insulating layer, a second insulating layer, a chip, and an encapsulant. The first insulating layer and second insulating layer are disposed on a first surface and a second surface of metal layer respectively. The first surface and second surface are opposite. The first insulating layer includes a first part and a second part separated from each other. An accommodating space is existed between the first part and the second part and a part of the first surface is exposed. The chip is accommodated in the accommodating space and disposed on the exposed part of the first surface. The encapsulant fills the spaces between the chip and the first part and between the chip and the second part to form the double-sided COF packaging structure.

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

The present invention provides for an interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly comprises a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within said flexible base layer, and at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer and which is configured to operably interface with said at least one active electronic circuit component and the at least one 1C component.

A bonding apparatus includes: an anisotropic conductive film (ACF) attachment unit which attaches a first ACF and a second ACF onto a display panel assembly; a compression unit which compresses a first chip-on-film (COF) on the first ACF and compresses a second COF on the second ACF; and a buffer unit which rotates the display panel assembly, on which the first ACF and the second COF are compressed, on a plane.

In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.