Provided is a package structure includes a first die, a first dielectric layer, a second dielectric layer and a carrier. The first dielectric layer covers a bottom surface of the first die. The first dielectric layer includes a first edge portion and a first center portion in contact with the bottom surface of the first die. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the first die. The second dielectric layer includes a second edge portion and a second center portion. The second edge portion is located on the first edge portion, and the second edge portion is thinner than the second center portion. The carrier is bonded to the first dielectric layer through a bonding film.

A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

The present invention relates to a film-shaped firing material (1) which contains: sinterable metal particles (10); a binder component (20) that is a solid at room temperature; and a liquid component (30) that is a liquid at room temperature, the liquid component having a boiling point from 300 to 450° C.

In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other. In forming the stacked substrate, in a state where the fourth main surface is bonded to the third main surface, a fifth main surface of the third substrate opposite to the fourth main surface is thinned.

A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.