A method includes: wetting a plurality of top dies disposed on a top wafer in a first wet clean tool located in a wet clean chamber; wetting a plurality of bottom dies disposed on a bottom wafer in a second wet clean tool located in the wet clean chamber, the plurality of bottom dies corresponding to the plurality of top dies, respectively; transferring the top wafer to a wafer-to-wafer bonding tool located in a wafer-to-wafer bonding chamber, without placing the top wafer in a first wafer container; transferring the bottom wafer to the wafer-to-wafer bonding tool, without placing the bottom wafer in a second wafer container; and bonding, by the wafer-to-wafer bonding tool, the top wafer to the bottom wafer.

A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

A substrate positioning apparatus includes a holder and a rotating device. The holder is configured to hold a substrate. The rotating device is configured to rotate the holder. The rotating device includes a rotation shaft, a bearing member, a base member, a driving unit and a damping device. The rotation shaft is fixed to the holder. The bearing member is configured to support the rotation shaft in a non-contact state. The bearing member is fixed on the base member. The driving unit is configured to rotate the rotation shaft. The damping device includes a rail connected to the base member and a slider connected to the rotation shaft, and is configured to produce a damping force against a relative operation between the rotation shaft and the base member by a resistance generated between the rail and the slider.

Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.

The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly; and forming a first dielectric layer on the first surface of the wafer. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.

An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.

A semiconductor wafer processing method, having: ablating a back side of a semiconductor wafer with a laser ablation process; and etching the back side of the semiconductor wafer with an etching process; wherein the laser ablation process forms a pattern in the back side of the semiconductor wafer; wherein the etching process preserves the pattern in the back side of the semiconductor wafer.

A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

The invention describes a fabricating method for fabricating semiconductor package device which includes the following steps: providing a wafer having a plurality of dies, wherein each of the dies is provided on a top surface thereof with a middle electric conducting structure and a solder ball; forming a molding structure having a flat top surface on a top side of the wafer; removing a part of the molding structure and exposing a part of each of the solder ball by plasma etching; performing a dicing process along a boundary of each of the dies to separate each of the dies so that the semiconductor package device is thus obtained.