Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

An electronic component module (100) includes a module board (10) having electronic components (40) mounted on at least one of a first surface (front surface) (12) and a second surface (back surface) (14), mold portions (22 and 23), and a shield (32). The mold portions (22 and 23) cover the mounted electronic components (40). The shield (32) covers at least a part of the mold portions (22 and 23) and the side surfaces of the module board (10). Protrusions (15) protruding from the side surfaces are formed on the module board (10). The shield (32) is separated by the protrusions (15).

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

Provided is a method for manufacturing a semiconductor device suitable for achieving low wiring resistance between semiconductor elements that is bonded via an adhesive layer and multi-layered. The method according to the present invention is as follows. First, a wafer laminate (W) is prepared, the wafer laminate (W) including a wafer (10) having a circuit forming surface (10a), a wafer (20) having a main surface (20a) and a back surface (20b), and an adhesive layer (30) containing an SiOC-based polymer. Then, a hole (H) is formed in the wafer laminate (W) by etching the wafer laminate (W) from the wafer (20) side via a mask pattern masking a portion of the main surface (20a) side of the wafer (20), the hole (H) extending through the wafer (20) and the adhesive layer (30) and reaching a wiring pattern (12b) in the wafer (10). Then, an insulating film (41) is formed on an inner surface of the hole (H). Then, the insulating film (41) on a bottom surface of the hole (H) is removed. Then, the wafer laminate (W) is subjected to a cleaning treatment (an oxygen plasma treatment and/or an Ar sputtering treatment). Then, a conductive portion is formed in the hole (H).

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

A temperature rise due to thermal interference between electronic components is suppressed. Electronic components (11a, 11b) are adjacently mounted on a circuit board (12). The circuit board (12) is fixed to a base (13). A rectangular convex portion (21) is provided on the base (13). The rectangular convex portion (21) is disposed so as to be located below the electronic components (11a, 11b) when the circuit board (12) is assembled to a housing (10). The rectangular convex portion (21) includes N concave portions (21a). The concave portions (21a) are arranged on a surface (21b) facing the region between the electronic components (11a, 11b).

The display device includes a flexible base layer including a first region and a second region located around the first; a display unit on one surface of the first region and including a light emitting element; a driving circuit on the second region and including a plurality of first bumps arranged in a first row and a plurality of second bumps arranged in a second row, the driving circuit includes a third bump in the first row and disposed outward relative to the plurality of first bumps, a first and second reference bump each disposed at a center of the plurality of first and second bumps that are disposed along a reference line defined in a column direction vertically intersecting a row direction, the remaining first and second bumps excluding the first reference bump and the second reference bump arranged to have a preset slope with respect to the reference line.

Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.

Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.