Semiconductor device including first semiconductor layer of a first conductivity type, second semiconductor layer of a second conductivity type at a surface of the first semiconductor layer, third semiconductor layer of the first conductivity type selectively provided at a surface of the second layer, and gate electrode embedded in a trench via a gate insulating film. The trench penetrates the second and third layers, and reaches the first layer. A thermal oxide film on the third layer has a thickness less than that of the gate insulating film. Also are an interlayer insulating film on the thermal oxide film, barrier metal on an inner surface of a contact hole selectively opened in the thermal oxide film and the interlayer insulating film, metal plug embedded in the contact hole on the barrier metal, and electrode electrically connected to the second and third layers via the barrier metal and the metal plug.

The present disclosure a method for manufacturing a metal-oxide-semiconductor (MOS) transistor device. The method includes steps of providing a substrate; forming a gate electrode over the substrate; forming a source region and a drain region in the substrate; depositing an isolating layer over the substrate and the gate electrode; forming a plurality of contact holes in the isolating layer to expose the gate electrode, the source region, and the drain region; forming a plurality of metal contacts in the gate electrode, the source region, and the drain region; depositing a contact liner in the contact holes; and depositing a conductive material in the contact holes, wherein the conductive material is surrounded by the contact liner.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF.sub.2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

A method of manufacturing a semiconductor device includes: forming an electron transit layer; forming an electron supply layer; forming a protective film; forming a zinc oxide film; forming a sacrifice layer; forming a first opening and a second opening in the sacrifice layer and the zinc oxide film; forming a third opening connecting to the first opening and a fourth opening connecting to the second opening; forming, by acid treatment using a weakly acidic solution, a first gap in a first portion exposed to the first opening of the zinc oxide film, and a second gap in a second portion exposed to the second opening of the zinc oxide film; forming, after the acid treatment, a source region on a bottom surface of the third opening and a drain region on a bottom surface of the fourth opening; and removing the zinc oxide film.

Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

A method of manufacturing a semiconductor device includes forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer, forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer, forming layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the layers of the first dielectric layer and the insertion layer to form a recess.

The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.

According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.