An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

The techniques relate to methods and apparatus for conductance measurement. A device includes a fluid chamber, at least one sensor element configured to sense an analyte, wherein the at least one sensor element is in fluid communication with the fluid chamber, and a set of one or more electrodes in fluid communication with the fluid chamber for sensing a conductance of a fluid in the fluid chamber.

According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other end portion. The third electrode end portion is between the first electrode and the third electrode other end portion. The first conductive member includes a first conductive member end portion and a first conductive member other end portion. The first conductive member end portion is between the first electrode and the first conductive member other end portion. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The first insulating member includes silicon and oxygen. The first insulating member includes a first element including at least one selected from the group consisting of nitrogen, aluminum, hafnium and zirconium at the third position.

Hybrid transparent conducting materials are disclosed which combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and the conductive nanostructures preferably are silver nanowires.

Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

A semiconductor device includes a semiconductor substrate, multiple trench gate structures and an emitter region. The semiconductor substrate includes: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed on the drift layer; and a collector layer of the second conductivity type, the collector layer disposed at a position opposite to the base layer with the drift layer sandwiched between the base layer and the collector layer. Each of the trench gate structures includes: a trench penetrating the base layer and reaching the drift layer; a gate insulation film is disposed at a wall surface of the trench; and a gate electrode disposed on the gate insulation film. The emitter region is disposed on a surface layer portion of the base layer and is in contact with the trench.

Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

The present disclosure provides a method for manufacturing a semiconductor structure having a vertical fin with an oxidized sidewall. The method of manufacturing the semiconductor structure includes the steps of providing a substrate having a bottom source/drain and a bottom cathode/anode; forming a channel fin on the bottom source/drain of the substrate and a vertical fin on the cathode/anode of the substrate; forming a top source/drain on the channel fin and a top cathode/anode on the vertical fin; forming a gate structure on the channel fin; and forming an oxidized sidewall on the vertical fin.

Nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.