A semiconductor substrate has an internal circuit, a plurality of first pads electrically connected to the internal circuit, and one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads and are not electrically connected to the internal circuit.

The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

Disclosed is a metal-semiconductor contact structure based on two-dimensional (2D) semimetal electrodes, including a semiconductor module and a metal electrode module, where the semiconductor module is a 2D semiconductor material, and the metal electrode module is a 2D semimetal material with no dangling bonds on its surface; the 2D semiconductor material and the 2D semimetal material are interfaced with a Van der Waals interface with a surface roughness of 0.01-1 nanometer (nm) and no dangling bonds on the surface, the 2D semiconductor material and the 2D semimetal material are spaced less than 1 nm apart.

Disclosed is a metal-semiconductor contact structure based on two-dimensional (2D) semimetal electrodes, including a semiconductor module and a metal electrode module, where the semiconductor module is a 2D semiconductor material, and the metal electrode module is a 2D semimetal material with no dangling bonds on its surface; the 2D semiconductor material and the 2D semimetal material are interfaced with a Van der Waals interface with a surface roughness of 0.01-1 nanometer (nm) and no dangling bonds on the surface, the 2D semiconductor material and the 2D semimetal material are spaced less than 1 nm apart.

A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a second electrode spaced from the first electrode and located over the semiconductor layer and connected to the semiconductor layer, an insulation film located over the semiconductor layer, and a third electrode interposed between the first electrode and the second electrode, and location over a portion of the insulation film. The insulation film includes a first layer located on the semiconductor layer and between the first electrode and the second electrode and comprising silicon nitride, and a second layer located on the first layer and between the first electrode and the third electrode as well as between the second electrode and the third electrode, and comprising silicon nitride and an amount of oxygen larger than the first layer.

Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.

Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.

A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.

An electrical assembly may include an electrical component, a first switch, and/or a second switch. The electrical component may include a closed state and an open state. The first switch may be connected in series with the second switch. The first switch and the second switch may be connected in parallel with the electrical component. The first switch and the second switch may be configured to provide a second electrical connection when the electrical component is in the open state. A method of operating an electrical assembly may include providing power from a power source to the electrical component, opening the electrical component, the first switch, and/or the second switch via a controller, closing a second electrical component via the controller, and/or providing a diagnostic current from the power source to a diagnostic load to determine a status of the power source.

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.