Gate-controlled quantum dots based on silicon-germanium (SiGe) alloy heterostructures are provided. Also provided are quantum computing systems incorporating the gate-controlled quantum dots. The quantum dots are formed in a semiconductor heterostructure in which a SiGe alloy quantum well is sandwiched between SiGe alloy barriers or between Ge barriers. The presence of germanium in the quantum dots increases the average valley splitting for quantum dots confined in the SiGe. As a result, the yield of quantum dots having a sufficiently high valley splitting for device applications is increased by the use of a SiGe alloy in the quantum well.

A quantum processing system is disclosed. In one embodiment, a quantum processing system comprises: a plurality of donor atoms positioned in a silicon crystal substrate, each donor atom positioned at a donor site; and a plurality of conductive control electrodes arranged about the donor atoms to operate the donor atoms as qubits. Where, at least two pairs of nearest neighbour donor atoms of the plurality of donor atoms are arranged along the [110] direction of the silicon crystal substrate and are configured to operate as qubits.

Methods, devices, and systems are described for storing and transferring quantum information. An example device may comprise at least one semiconducting layer, one or more conducting layers configured to define at least two quantum states in the at least one semiconducting layer and confine an electron in or more of the at least two quantum states, and a magnetic field source configured to generate an inhomogeneous magnetic field. The inhomogeneous magnetic field may cause a first coupling of an electric charge state of the electron and a spin state of the electron. The device may comprise a resonator configured to confine a photon. An electric-dipole interaction may cause a second coupling of an electric charge state of the electron to an electric field of the photon.

A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions. In addition, the edge of the raised diffusion layer may be placed either in the gate region or the active layer region.

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

Processor elements are described herein. A processor element comprises a silicon layer. The processor element further comprises one or more conductive electrodes. The processor element further comprises dielectric material having a non-uniform thickness, the dielectric material disposed at least between the silicon layer and the one or more conductive electrodes. In use, when a bias potential is applied to one or more of the conductive electrodes, the positioning of the one or more conductive electrodes and the non-uniform thickness of the dielectric material together define an electric field profile to induce a quantum dot at an interface between the silicon layer and the dielectric layer. Methods are also described herein.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A method for the patterning and control of single electrons on a surface is provided that includes implementing scanning tunneling microscopy hydrogen lithography with a scanning probe microscope to form charge structures with one or more confined charges; performing a series of field-free atomic force microscopy measurements on the charge structures with different tip heights, where interaction between the tip and the confined charge are elucidated; and adjusting tip heights to controllably position charges within the structures to write a given charge state. The present disclose also provides a Gibb's distribution machine formed with the method for the patterning and control of single electrons on a surface. A multi bit true random number generator and neural network learning hardware formed with the above described method are also provided.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.