A device is disclosed that includes a semiconductor substrate, a bottom electrode disposed on a first surface of the semiconductor substrate, an insulating layer disposed on a second surface that is opposite to the first surface, of the semiconductor substrate, a current-to-voltage converter, a first electrode and a second electrode that are separate from each other and disposed on the insulating layer. The first electrode is configured to be applied with an input signal, and the second electrode is configured to output an output current signal that is associated with the input signal, the input signal is configured to have a voltage level that is variable, and the output current signal is configured to have a peak current value and a valley current value. The current-to-voltage converter is configured to receive the output current signal to generate an output voltage signal.

A device is disclosed that includes a semiconductor substrate, a bottom electrode disposed on a first surface of the semiconductor substrate, an insulating layer disposed on a second surface that is opposite to the first surface, of the semiconductor substrate, a current-to-voltage converter, a first electrode and a second electrode that are separate from each other and disposed on the insulating layer. The first electrode is configured to be applied with an input signal, and the second electrode is configured to output an output current signal that is associated with the input signal, the input signal is configured to have a voltage level that is variable, and the output current signal is configured to have a peak current value and a valley current value. The current-to-voltage converter is configured to receive the output current signal to generate an output voltage signal.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A device is disclosed that includes an insulating layer, a first electrode, a second electrode, and a bottom electrode. The insulating layer is disposed on a first surface of a substrate. The first electrode and the second electrode are disposed on a first surface of the insulating layer. The first electrode receives an input signal, and the second electrode outputs, in response to the input signal, an output signal. The bottom electrode is disposed on a second surface, opposite to the first surface, of the substrate and receives an operating voltage to modify a frequency of the output signal.

A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.

A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A semiconductor structure can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and capacitor pillar structures vertically extending through the first alternating stack. Each of the capacitor pillar structures can include a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric. A first electrode layer of a capacitor includes the semiconductor material portions, and a second electrode layer of the capacitor includes the electrically conductive layers. Alternatively or additionally, a first dielectric fill material portion can extend through the alternating stack and can include a plurality of capacitor via cavities. A capacitor can be provided within the plurality of capacitor via cavities.

Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.