A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

A magnetoresistance effect element according to an embodiment includes: a spin orbit torque wiring extending in a first direction; a laminated body laminated on the spin orbit torque wiring and having a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; a conductive layer in contact with a side of the laminated body opposite to the spin orbit torque wiring; and a heat dissipation layer separated from the laminated body in the first direction and connected to the spin orbit torque wiring and the conductive layer.

A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a buffer layer, a seed layer disposed over the buffer layer, a reference layer disposed over the seed layer, a tunnel barrier layer disposed over the reference layer and a free layer disposed over the tunnel barrier layer. The seed layer includes a Cobalt (Co)-based film. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.

The present disclosure provides a semiconductor structure, including an N.sup.th metal layer over a transistor region, where N is a natural number, and a bottom electrode over the N.sup.th metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1).sup.th metal layer over the top electrode. The first width is greater than the third width.

A random number generation unit and a computing system using the same, the unit including a magnetic tunnel junction element and being capable of developing the characteristics required for the execution of probabilistic computing and operating at a higher speed. A magnetic tunnel junction element includes a fixed layer having a ferromagnet and having a magnetization direction fixed substantially, a free layer having a ferromagnet and having a magnetization direction varying with a first time constant, and a barrier layer disposed between the layers configured with an insulator. The magnetic tunnel junction element has a shift magnetic field of an absolute value of 20 millitesla or smaller. The fixed layer has a plurality of ferromagnetic and non-magnetic coupling layers laminated one upon another, and ferromagnetic layers adjacent to each other among the respective ferromagnetic layers are coupled in terms of magnetization by the non-magnetic coupling layers in an antiparallel manner.

A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or combinations thereof, in which M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

A semiconductor structure includes a bottom MTJ stack with a bottom fixed layer, a bottom barrier layer, and a bottom free layer. The semiconductor structure also includes a top MTJ stack with a top fixed layer, a top barrier layer, and a top free layer. Additionally, the semiconductor structure also includes a spin-Hall effect (SHE) rail with a dielectric, a top heavy metal layer, and a bottom heavy metal layer.