A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Electronic devices and more particularly diamond-based electronic devices and corresponding contact structures are disclosed. Electrical contact structures to diamond layers, including n-type, phosphorus doped single-crystal diamond are disclosed. In particular, electrical contact structures are formed through an arrangement of one or more nanostructured carbon layers with high nitrogen incorporation that are provided between metal contacts and n-type diamond layers in diamond-based electronic devices. Nanostructured carbon layers may be configured to mitigate reduced phosphorus incorporation in n-type diamond layers, thereby providing low specific contact resistances for corresponding devices. Diamond p-i-n diodes for direct electron emission applications are also disclosed that include electrical contact structures with nanostructured carbon layers.

In a first cell region of a semiconductor substrate, a first semiconductor element is formed. In a second cell region of semiconductor substrate, a second semiconductor element is formed. First semiconductor element includes a first electrode and a first p region. Second semiconductor element includes a second electrode and a second p region. First electrode and second electrode are separated from each other. First p region and second p region are separated from each other.

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

A semiconductor transistor device includes a GaN transistor including a drain, a gate, and a source, the GaN transistor having a driving voltage applied across the gate and the source and configured to switch between an on-voltage associated with an on-state of the GaN transistor and an off-voltage associated with an off-state of the GaN transistor. The semiconductor transistor device further includes a variable gate-source resistor connected between the gate and the source and having a variable resistance that varies in response to changes in the driving voltage when switching between the on-state and the off-state of the GaN transistor.

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices. The method includes forming first, second, and third nanosheet stacks, removing sacrificial layers of the first, second, and third nanosheet stacks, and depositing an interfacial layer and a high-k layer within the first, second, and third nanosheet stacks. The method further includes depositing a first work function metal (WFM) layer within the first nanosheet stack having a first thickness, depositing a second WFM layer within the second nanosheet stack having a second thickness, wherein the second thickness is greater than the first thickness, depositing a third WFM layer within the third nanosheet stack having a third thickness, wherein the third thickness is greater than the second thickness, depositing a dipole material, and diffusing the dipole material into the IL to provide different gate threshold voltages for the plurality of FET devices.

A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.