A high efficiency configuration for a string of solar cells comprises series-connected solar cells arranged in an overlapping shingle pattern. Front and back surface metallization patterns may provide further increases in efficiency.

Example embodiments relate to controlling detection time in photodetectors. An example embodiment includes a device. The device includes a substrate. The device also includes a photodetector coupled to the substrate. The photodetector is arranged to detect light emitted from a light source that irradiates a top surface of the device. A depth of the substrate is at most 100 times a diffusion length of a minority carrier within the substrate so as to mitigate dark current arising from minority carriers photoexcited in the substrate based on the light emitted from the light source.

A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer have different conductivity types. The method also includes forming a graphene layer overlying the plurality of nanopillars. The graphene layer is connected to each of the plurality of nanopillars.

A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure.

A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure.

A photovoltaic cell is proposed. The photovoltaic cell includes a substrate of semiconductor material, and a plurality of contact terminals each one arranged on a corresponding contact area of the substrate for collecting electric charges being generated in the substrate by the light. For at least one of the contact areas, the substrate includes at least one porous semiconductor region extending from the contact area into the substrate for anchoring the whole corresponding contact terminal on the substrate. In the solution according to an embodiment of the invention, each porous semiconductor region has a porosity decreasing moving away from the contact area inwards the substrate. An etching module and an electrolytic module for processing photovoltaic cells, a production line for producing photovoltaic cells, and a process for producing photovoltaic cells are also proposed.

The invention relates to quantum dot and photodetector technology, and more particularly, to quantum dot infrared photodetectors (QDIPs) and focal plane array. The invention further relates to devices and methods for the enhancement of the photocurrent of quantum dot infrared photodetectors in focal plane arrays.

Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

A semiconductor device includes element regions which each include a first region of a first conductivity type, a second region of the first conductivity type on the first region and having a higher impurity concentration than that of the first region, a third region of a second conductivity type on the second region. The second region is between the first and third regions in a first direction. A first insulating portion surrounds each element region in a first plane. A fourth region of the first conductivity type surrounds each element region and the first insulating portion in the first plane. The fourth region has a higher impurity concentration than that of the first region. A quenching structure is above a part of the fourth region in the first direction and electrically connected to the third region.