Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.

A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing an optoelectronic semiconductor chip with a radiation passage surface on a connection carrier, applying a deformable spacer to the radiation passage surface of the semiconductor chip, inserting the connection carrier with the semiconductor chip into a cavity of a tool, deforming, by the tool, the deformable spacer and encapsulating the semiconductor chip with a casting compound.

A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing an optoelectronic semiconductor chip with a radiation passage surface on a connection carrier, applying a deformable spacer to the radiation passage surface of the semiconductor chip, inserting the connection carrier with the semiconductor chip into a cavity of a tool, deforming, by the tool, the deformable spacer and encapsulating the semiconductor chip with a casting compound.

The invention relates to a method for fabricating a thermal detector (1), comprising the following steps: forming a first stack (10), comprising a thermal detector (20), a mineral sacrificial layer (15) and a thin encapsulation layer (16) having a lateral vent (17.1); forming a second stack (30), comprising a thin sealing layer (33) and a getter portion (34); eliminating the mineral sacrificial layer (15); assembling by direct bonding the thin sealing layer (33), brought into contact with the thin encapsulation layer (16) and blocking the lateral vent (17.1), the getter portion (34) being located in the lateral vent (17.1).

The invention relates to a method for fabricating a thermal detector (1), comprising the following steps: forming a first stack (10), comprising a thermal detector (20), a mineral sacrificial layer (15) and a thin encapsulation layer (16) having a lateral vent (17.1); forming a second stack (30), comprising a thin sealing layer (33) and a getter portion (34); eliminating the mineral sacrificial layer (15); assembling by direct bonding the thin sealing layer (33), brought into contact with the thin encapsulation layer (16) and blocking the lateral vent (17.1), the getter portion (34) being located in the lateral vent (17.1).

An infrared image sensor includes a first integrate circuit (IC), a bolometer disposed on or above one surface of the first IC configured to detect infrared rays passing through a lens module, a via electrically connecting the first IC and the bolometer, and a reflective layer disposed between the first IC and the bolometer, wherein the first IC includes at least one of a read-out (RO) element configured to perform analog processing for the bolometer to generate infrared sensing information and an image signal process (ISP) element configured to perform digital processing based on the bolometer to generate infrared image information, and at least one of an autofocusing (AF) control element and an optical image stabilization (OIS) control element configured to adjust a positional relationship between the lens module and the bolometer.