A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

A photoelectric conversion device includes: a substrate; a first photoelectric conversion element including a first substrate electrode, a first photoelectric conversion layer, and a first counter electrode; a second photoelectric conversion element including a second substrate electrode, a second photoelectric conversion layer, and a second counter electrode; and a connection including a groove, a conductive portion and a conductive layer, the conductive portion being provided in the groove and including a part of the first counter electrode, and the conductive portion and the conductive layer electrically connecting the first counter electrode and the second substrate electrode. The conductive layer overlaps the first counter electrode on an edge of the groove, and a total thickness of the conductive portion and the conductive layer is larger than a thickness of the first counter electrode.

Separation of individual strips from a solar cell workpiece, is accomplished by excluding a junction (e.g., a homojunction such as a p-n junction, or a heterojunction such as a p-i-n junction) from regions at which separation is expected to occur. According to some embodiments, the junction is excluded by physical removal of material from inter-strip regions of the workpiece. According to other embodiments, exclusion of the junction is achieved by changing an effective doping level (e.g., counter-doping, deactivation) at inter-strip regions. For still other embodiments, the junction is never formed at inter-strip regions in the first place (e.g., using masking during original dopant introduction). By imposing distance between the junction and defects arising from separation processes (e.g., backside crack propagation), losses attributable to electron-hole recombination at such defects are reduced, and collection efficiency of shingled modules is enhanced.

Photovoltaic devices and methods for fabricating a photovoltaic devices. The method includes applying a coating layer that surrounds each of a plurality of silicon particles. The method also includes implanting the plurality of silicon particles into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer. The method further includes removing a portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles. The method also includes placing an insulator layer on the surface of the substrate layer. The method further includes placing a selective carrier transport layer on the exposed portion of each of the plurality of silicon particles.

A method of forming an optical thin film, comprises providing an assembly comprising a layer of semiconductor material deposited on a substrate, the semiconductor material comprising a compound of at least one metal and a group VI element; depositing a masking layer onto the layer of semiconductor material, the masking layer being patterned to expose one or more regions of the layer of semiconductor material; applying to the assembly a plasma of the group VI element in order to cause indiffusion of the group VI element into the semiconductor material in the exposed regions while the masking layer blocks indiffusion in unexposed regions, the indiffusion causing a reduction in carrier density in the semiconductor material; and removing the masking layer; thereby forming, from the layer of semiconductor material, an optical thin film having a variation in carrier density and corresponding variation in optical properties matching the patterning of the masking layer in a plane parallel to the substrate.

Disclosed herein are methods for using cracked film lithography (CFL) for patterning transparent conductive metal grids. CFL can be vacuum- and Ag-free, and it forms more durable grids than nanowire approaches.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

The invention provides an optoelectronic device comprising a photoactive region, which photoactive region comprises: an n-type region comprising at least one n-type layer; a p-type region comprising at least one p-type layer; and, disposed between the n-type region and the p-type region: a layer of a perovskite semiconductor without open porosity. The perovskite semiconductor is generally light-absorbing. In some embodiments, disposed between the n-type region and the p-type region is: (i) a first layer which comprises a scaffold material, which is typically porous, and a perovskite semiconductor, which is typically disposed in pores of the scaffold material; and (ii) a capping layer disposed on said first layer, which capping layer is said layer of a perovskite semiconductor without open porosity, wherein the perovskite semiconductor in the capping layer is in contact with the perovskite semiconductor in the first layer. The layer of the perovskite semiconductor without open porosity (which may be said capping layer) typically forms a planar heterojunction with the n-type region or the p-type region. The invention also provides processes for producing such optoelectronic devices which typically involve solution deposition or vapour deposition of the perovskite. In one embodiment, the process is a low temperature process; for instance, the entire process may be performed at a temperature or temperatures not exceeding 150° C.

The present disclosure relates to a photodiode, a method for preparing the same, and an electronic device. The photodiode includes: a first electrode layer and a semiconductor structure that are stacked, a surface of the semiconductor structure away from the first electrode layer having a first concave-convex structure; and a second electrode layer arranged on a surface of the semiconductor structure away from the first electrode layer, a surface of the second electrode layer away from the first electrode layer having a second concave-convex structure.

A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected.