The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1-x1-y1)(Al.sub.q1Ga.sub.1-q1).sub.2O.sub.4 wherein 0≤x1≤1, 0≤y1≤1 and 0≤q1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1-x2-y2)(Al.sub.q2Ga.sub.1-q2).sub.2O.sub.4 wherein 0≤x2≤1, 0≤y2≤1 and 0≤q2≤1. In some cases, at least one condition selected from x1≠x2, y1≠y2, and q1≠q2 is satisfied.

The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising Li(Al.sub.x1Ga.sub.1−x1)O.sub.2 wherein 0≤x1≤1; and a second epitaxial oxide layer comprising (Al.sub.x2Ga.sub.1−x2).sub.2O.sub.3 wherein 0≤x2≤1.

The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1−x1−yl).sub.2GeO.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1. In some cases, either: x1≠x2 and y1=y2; x1=x2 and y1≠y2; or x1≠x2 and y1≠y2. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Mg.sub.x1Zn.sub.1−x1)(Al.sub.y1Ga.sub.1−y1).sub.2O.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1.

A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As.

A light-emitting device, includes: a semiconductor stack, including a top surface, wherein the top surface includes a first region and a second region which are coplanar; a current barrier layer formed on the first region, wherein the current barrier layer includes an insulating material; and a transparent conductive layer formed on the current barrier layer and the second region; and a first electrode formed on the transparent conductive layer; wherein the current barrier layer includes: an electrode region at a position corresponding to the first electrode, having a shape substantially the same as the first electrode; and a plurality of extension regions extending from the electrode region and not covered by the first electrode.

Embodiments disclose LEDs that operate using impact ionization. Devices include a first conductivity type layer, an intrinsic layer, and an impact ionization layer. In some embodiments, a charge layer is on the intrinsic layer, where the charge layer comprises a first material and has a net charge. The impact ionization layer comprises a second material. The charge layer forms a barrier for transporting carriers until a bias of at least 1.5 times a bandgap of the second material is applied, and a resulting electric field in the impact ionization layer is greater than or equal to a threshold for the second material. In some embodiments the first intrinsic layer is on the first conductivity type layer and is made of the first material, and a compositional step at an interface between the intrinsic layer and the impact ionization layer creates a barrier for transporting carriers.

An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.