A microdevice structure comprising at least part of an edge of a microdevice is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

The present invention relates to a light emitting device comprising a first main layer of an electrically conducting material, a second main layer of an electrically conducting material and a light emitting unit between the first main layer and the second main layer, wherein the light emitting unit comprises a light emitting layer, and wherein the first main layer and/or the second main layer has a light exit orifice aligned with a section of the light emitting layer. The light emitting device can utilise impact ionisation to emit UV-C light.

A light emitting display device includes a plurality of sub-pixels each including an emission area and a non-emission area, an anode including a first transparent electrode and a second transparent electrode at each of the plurality of sub-pixels, to overlap with the emission area and a portion of the non-emission area, a plurality of protrusion patterns inside an edge line of the second transparent electrode between the first transparent electrode and the second transparent electrode, and a bank to expose the emission area and a first area of the non-emission area.

A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

Light-emitting devices are disclosed. In some embodiments, the devices may emit light when a tunneling current is generated within the device.

As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

Disclosed are a light emitting element, which may reduce power consumption, and a light emitting device including the same. The light emitting element includes an active layer emitting light by recombination of electrons and holes respectively supplied from first and second electrodes, and a control electrode controlling light emission of the active layer. Therefore, a transistor conventionally connected to the light emitting element may be omitted and thus power loss generated due to the transistor may be prevented.

A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

The present disclosure proposes a method for fabricating a graphene luminous component. The method includes: supplying a bottom substrate on which metallic gates are arranged at intervals; forming a first insulating protective layer covering the bottom substrate and the metallic gate; forming a graphene luminous layer with graphene luminous blocks on the first insulating protective layer; forming a graphene source and a graphene drain arranged at intervals on each of graphene luminous blocks; forming a second insulating protective layer covering the first insulating protective layer, the graphene luminous layer, the graphene source, and the graphene drain; and laminating a top substrate onto the second insulating protective layer. The present disclosure proposes a gate fabricated from metal, a source, a drain, and a luminous layer fabricated from graphene for the graphene luminous component. Therefore, the luminous efficiency of the luminous component is enhanced with lower power consumption.