Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

An SiC substrate processing method for producing an SiC substrate from an SiC ingot. The SiC substrate processing method includes a separation layer forming step of setting a focal point of a laser beam having a transmission wavelength to SiC inside the SiC ingot at a predetermined depth from the upper surface of the SiC ingot and next applying the laser beam LB to the SiC ingot to thereby form a separation layer for separating the SiC substrate from the SiC ingot, a substrate attaching step of attaching a substrate to the upper surface of the SiC ingot, and a separating step of applying an external force to the separation layer to thereby separate the SiC substrate with the substrate from the SiC ingot along the separation layer.

The present application provides a graphene light emitting transistor, including: a gate electrode disposed on a substrate; a gate insulating layer disposed on the substrate and the gate electrode; a source electrode and a drain electrode disposed on the gate insulating layer, wherein the source electrode and the drain electrode are formed by graphene; a graphene oxide layer disposed on the gate insulating layer and located between the source electrode and the drain electrode; a graphene quantum dot layer disposed on the graphene oxide layer, the source electrode and the drain electrode; and a water and oxygen resistant layer disposed on the graphene quantum dot layer. The present application also provides a method of fabricating the graphene light emitting transistor and an active graphene light emitting display apparatus having the graphene light emitting transistor.

A light-emitting device according to one embodiment includes: a substrate; a graphite thin film disposed on the substrate; and an electrode provided on a second surface of the graphite thin film on an edge portion of the graphite thin film, the second surface of the graphite thin film being opposite from a first surface of the graphite thin film, the first surface of the graphite thin film opposed to the substrate. A plurality of protrusions for supporting the graphite thin film is formed on a surface of the substrate opposed to the graphite thin film, at least over an entire region where the substrate and a portion of the graphite thin film other than the edge portion overlap each other when viewed along a thickness direction of the substrate.

An optical device includes a substrate, an electronic component, a lid and a barrier. The electronic component is disposed on the substrate. The electronic component has an active surface faces away from the substrate. The lid is disposed on the substrate. The lid has a wall structure extending toward the active surface of electronic component and is spaced apart from the active surface of the electronic component. The barrier is disposed on the active surface of the electronic component and is spaced apart from the wall structure of the lid.

A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.

The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.

The present disclosure falls into the field of optoelectronics, particularly, includes the design, epitaxial growth, fabrication, and characterization of Laser Diodes (LDs) operating in the ultraviolet (UV) to infrared (IR) spectral regime on patterned substrates (PSs) made with (formed on) low cost, large size Si, or GaN on sapphire, GaN, and other wafers. We disclose three types of PSs, which can be universal substrates, allowing any materials (III-Vs, II-VIs, etc.) grown on top of it with low defect and/or dislocation density.

A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.

A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an active device layer on the superlattice comprising at least one active semiconductor device.