An optoelectronic device including a crystalline semiconductor layer based on GeSn and including a pin junction. This formed semiconductor layer includes a base portion; a single-crystal intermediate portion having an average value x.sub.pi1 of proportion of tin less than x.sub.ps1, thus forming a barrier region against charge carriers flowing in an upper portion; and the single-crystal upper portion including a homogeneous medium with a proportion of tin x.sub.ps1, and vertical structures having an average value x.sub.ps2 of proportion of tin greater than x.sub.ps1, thus forming regions for emitting or for receiving infrared radiation.

Patterned substrates and optoelectronic devices (UV laser diode, UV LED, and sensors grown on silicon substrate) formed on these patterned substrates are described. The method of making patterned substrates are described. Examples of making laser diodes on these patterned substrates described in detail. The PSs can be fabricated by either combination of e-beam lithography and wet-chemical etching or combination of e-beam lithography and dry etching or through Nanoimprint transfer of master mold patterns to various wafers followed by etching.

The physical and chemical properties of surfaces can be controlled by bonding nanoparticles, microspheres, or nanotextures to the surface via inorganic precursors. Surfaces can acquire a variety of desirable properties such as antireflection, antifogging, antifrosting, UV blocking, and IR absorption, while maintaining transparency to visible light. Micro or nanomaterials can also be used as etching masks to texture a surface and control its physical and chemical properties via its micro or nanotexture.

A method for manufacturing a light-emitting diode (LED) includes plural steps as follows. A first type semiconductor layer is formed. A second type semiconductor layer is formed on the first type semiconductor layer. An impurity is implanted into a first portion of the second type semiconductor layer. The concentration of the impurity present in the first portion of the second type semiconductor layer is greater than the concentration of the impurity present in a second portion of the second type semiconductor layer after the implanting, such that the resistivity of the first portion of the second type semiconductor layer is greater than the resistivity of the second portion of the second type semiconductor layer.

A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.

A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometers and 250 nanometers, inclusive, applying the wafer (1) to a film (11), at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated. A semiconductor chip, a component and a method for producing the latter are also provided.

A graphene light emitting display and a method of manufacturing the same are disclosed. The method comprises: manufacturing a graphene oxide (GO) thin film on a surface of a substrate with a thin film transistor formed thereon; providing a photomask corresponding to the GO thin film to form a source electrode, a drain electrode and a graphene quantum dot layer of a graphene light emitting transistor; and wherein the photomask includes: a complete transparent part corresponding to the region in which the source electrode and the drain electrode are located; a light blocking part corresponding to the region in which the thin film transistor is located; and a semitransparent part corresponding to the region in which the graphene quantum dot layer is located; wherein an insulating layer and a water and oxygen isolating layer are formed sequentially on a surface of the substrate with the graphene light emitting transistor formed thereon.

The present application provides a graphene light emitting transistor, including: a gate electrode disposed on a substrate; a gate insulating layer disposed on the substrate and the gate electrode; a source electrode and a drain electrode disposed on the gate insulating layer, wherein the source electrode and the drain electrode are formed by graphene; a graphene oxide layer disposed on the gate insulating layer and located between the source electrode and the drain electrode; a graphene quantum dot layer disposed on the graphene oxide layer, the source electrode and the drain electrode; and a water and oxygen resistant layer disposed on the graphene quantum dot layer. The present application also provides a method of fabricating the graphene light emitting transistor and an active graphene light emitting display apparatus having the graphene light emitting transistor.

A method of manufacturing a semiconductor element includes: providing a semiconductor stack including: a silicon substrate containing a first impurity of a first conductivity type that is one of p-type and n-type, at a first concentration, and a silicon semiconductor layer provided on the silicon substrate, the silicon semiconductor layer including: a first silicon semiconductor layer containing a second impurity of the first conductivity type at a second concentration that is lower than the first concentration, and a second silicon semiconductor layer containing a third impurity of a second conductivity type that is the other of p-type and n-type; and irradiating the silicon semiconductor layer with light having a predetermined peak wavelength in a presence of a forward current flowing through the silicon semiconductor layer such that the third impurity is diffused. The predetermined peak wavelength is longer than a wavelength corresponding to a magnitude of a bandgap of silicon.

In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.