In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in places between the connection layer and the current distribution layer.

In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in places between the connection layer and the current distribution layer.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.

A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.

A method for growing an electron-blocking layer, an epitaxial layer, and an LED chip are provided in the present disclosure. The epitaxial layer includes an N-type semiconductor layer, an active layer, a P-type semiconductor layer, and an electron-blocking layer. The electron-blocking layer is disposed between the active layer and the P-type semiconductor layer, and the N-type semiconductor layer is disposed on one side of the active layer away from the electron-blocking layer. The electron-blocking layer includes a proximal aluminum barrier layer close to the active layer, a distal aluminum barrier layer close to the P-type semiconductor layer, and an indium well layer disposed between the proximal aluminum barrier layer and the distal aluminum barrier layer. The content of aluminum component in the distal aluminum barrier layer is lower than the content of aluminum component in the proximal aluminum barrier layer.

A light emitting element includes a light emitting element core including a first area and a second area surrounding the first area. The light emitting element core includes a first semiconductor layer doped with a first dopant, a second semiconductor layer disposed on the first semiconductor layer and doped with a second dopant, an element active layer disposed between the first semiconductor layer and the second semiconductor layer; and a third semiconductor layer disposed between the element active layer and the second semiconductor layer and doped with the second dopant. The second area of the light emitting element core is located on an outer circumference of the light emitting element core and includes an outer surface of the light emitting element core. A doping concentration of the second dopant of the third semiconductor layer is lower than a defect density of the second area of the light emitting element core.

A light emitting element includes, successively from a lower side to an upper side, a first light emitting part having a first active layer, a tunnel junction part, and a second light emitting part having a second active layer. The first active layer includes a plurality of first well layers, and a first barrier layer positioned between two adjacent first well layers among the first well layers. The second active layer includes a plurality of second well layers, and a second barrier layer positioned between two adjacent second well layers among the second well layers. The second barrier layer is a nitride semiconductor layer containing an n-type impurity and gallium, and has an n-type impurity concentration higher than that of the first barrier layer. An n-type impurity concentration peak in the second barrier layer is located on a first light emitting part side.

In a general aspect, an LED structure may include regrown p-type layers and have a mesa structure formed on a substrate. The mesa structure may include preparation layers, an active multiple quantum well (MQW) structure, a first electron blocking layer (EBL), and one or more first p-type layers stacked in a c-plane direction. The sidewalls of the mesa may be substantially vertical or may exhibit a sloped profile. A second EBL may be conformally deposited over the mesa structure, followed by one or more second p-type layers deposited over the conformal second EBL layer. The second EBL and/or second p-type layer(s) deposited over the mesa structure may be referred to herein as regrown layers.