A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

A method for homogenizing the height of a plurality of wires from the plurality of wires erected on a face of a substrate, the method including a first step of coating the face of the substrate including the plurality of wires with a first film, the first film embedding the plurality of wires over a first height; a second step of coating the first film with a second film, the second film embedding at least one part of the plurality of wires over a second height; a step of removing the second film, the part of the wires of the plurality of wires embedded in the second film being removed at the same time as the second film, a mechanical stress between the first film and the second film being exerted during the removal step.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

A light emitting diode device has a bulk gallium and nitrogen containing substrate with an active region. The device has a lateral dimension and a thick vertical dimension such that the geometric aspect ratio forms a volumetric diode that delivers a nearly uniform current density across the range of the lateral dimension.

A method of manufacturing a LED precursor and a LED precursor is provided. The LED precursor is manufactured by forming a monolithic growth stack having a growth surface and forming a monolithic LED stack on the growth surface. The monolithic growth stack comprises a first semiconducting layer comprising a Group III-nitride, a second semiconducting layer, and third semi-conducting layer. The second semiconducting layer comprises a first Group III-nitride including a donor dopant such that the second semiconducting layer has a donor density of at least 5×1018 cm-3. The second semiconducting layer has an areal porosity of at least 15% and a first in-plane lattice constant. The third semiconducting layer comprises a second Group III-nitride different to the first Group-III-nitride. The monolithic growth stack comprises a mesa structure comprising the third semiconducting layer such that the growth surface comprises a mesa surface of third semiconducting layer and a sidewall surface of the third semiconducting layer encircling the mesa surface. The sidewall surface of the third semiconducting layer is inclined relative to the mesa surface. The mesa surface of the third semiconducting layer has a second in-plane lattice constant which is greater than the first in-plane lattice constant.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

A method of removing a substrate from III-nitride based semiconductor layers with a cleaving technique. A growth restrict mask is formed on or above a substrate, and one or more III-nitride based semiconductor layers are grown on or above the substrate using the growth restrict mask. The III-nitride based semiconductor layers are bonded to a support substrate or film, and the III-nitride based semiconductor layers are removed from the substrate using a cleaving technique on a surface of the substrate. Stress may be applied to the III-nitride based semiconductor layers, due to differences in thermal expansion between the III-nitride substrate and the support substrate or film bonded to the III-nitride based semiconductor layers, before the III-nitride based semiconductor layers are removed from the substrate. Once removed, the substrate can be recycled, resulting in cost savings for device fabrication.