In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

A memory device includes a semiconductor substrate, an isolation structure, and an anti-fuse structure. The isolation structure is disposed in the semiconductor substrate. The anti-fuse structure is disposed in the isolation structure and includes a first electrode and a second electrode. The second electrode is disposed adjacent to the first electrode. Both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate.

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

A memory device includes a semiconductor substrate, an isolation structure, and an anti-fuse structure. The isolation structure is disposed in the semiconductor substrate. The anti-fuse structure is disposed in the isolation structure and includes a first electrode and a second electrode. The second electrode is disposed adjacent to the first electrode. Both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate.

A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.