A marking structure where marking visibility is improved is provided. In a semiconductor device having a marking structure, the marking structure includes: a body for marking having a surface; a first mark group having a first concave portion formed in the surface; a second mark group having a second concave portion formed adjacent to the first concave portion in the surface. The first concave portion and the second concave portion differ in shape so that they may cause light reflection differently. Thus, visibility of the marking structure can be improved.

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

An electronic apparatus includes a display panel including a base substrate including an active area and a peripheral area adjacent to the active area, pixels on the active area, pads on the peripheral area and arranged in a first direction, signal lines connecting the pixels to the pads, and a vernier mark on the peripheral area and spaced apart from the pads and the signal lines, a circuit board on the display panel and including a base film, and leads on the base film and overlapping with the pads in a plan view, and a conductive adhesive member extending in the first direction and between the display panel and the circuit board to connect the pads to the leads. The conductive adhesive member overlaps with the vernier mark when viewed in a second direction intersecting the first direction.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

A semiconductor device includes a monocrystalline substrate of a material which does not have a liquid phase at atmospheric pressure, and an identification mark disposed on or in the substrate comprising an amorphous region of the material or a region of the material deviated from stoichiometry.

A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.

A dicing sheet with a protective film forming layer has a substrate film, an adhesive layer, and a protective film forming layer, and at a minimum, the adhesive layer is formed in an area surrounding the protective film forming layer in a planar view, and the substrate film has the following characteristics (a)-(c): (a) the melting point either exceeds 130° C. or the film has no melting point; (b) the thermal contraction rate under conditions of heating at 130° C. for two hours is from −5 to +5%, and (c) the degree of elongation-to-break in the MD direction and the CD direction is at least 100%, and the stress at 25% is no more than 100 MPa.

A polishing composition eliminating protrusions around a laser mark in wafer polishing processes, the manufacturing method therefor and a polishing method using the composition. The polishing composition including silica particles and water, wherein: the composition includes a tetraalkylammonium ion such that the mass ratio of the ion to SiO.sub.2 of the silica particles is 0.400 to 1.500:1, and the mass ratio of SiO.sub.2 dissolved in the polishing composition to SiO.sub.2 is 0.100 to 1.500:1; the tetraalkylammonium ion is derived from a compound selected from the group made of an alkali silicate, a hydroxide, a carbonate, a sulfate, and a halide while the ion is contained in the polishing composition in 0.2% by mass to 8.0% by mass; and the dissolved SiO.sub.2 is derived from a tetraalkylammonium silicate, a potassium silicate, a sodium silicate, or a mixture of any of these.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.