Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

A component mounting system for mounting a component on a substrate, the mounting system comprising a component supplying unit configured to supply the component; a substrate holding unit configured to hold the substrate in an orientation such that a mounting face for mounting the component on the substrate is facing vertically downward; a head configured to hold the component from vertically below; and a head drive unit that, by causing vertically upward movement of the head holding the component, causes the head to approach the substrate holding unit to mount the component on the mounting face of the substrate.

A circuit board includes an interconnect and an insulating layer that covers the interconnect. The interconnect includes a first interconnect that is formed to serve as a recognition mark of which planar shape is a predetermined shape. The insulating layer has a through-hole of which planar shape is variant and that penetrates the insulating layer in a thickness direction of the insulating layer such that an entire upper surface of the first interconnect is exposed. The through-hole includes a first through-hole of which planar shape is a predetermined shape and that penetrates the insulating layer in the thickness direction such that the entire upper surface of the first interconnect is exposed and a second through-hole that serves as part of an inner wall surface of the first through-hole and that penetrates the insulating layer in the thickness direction.

A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.

A method of manufacturing a silicon carbide semiconductor device. The method includes epitaxially growing an epitaxial layer on a starting substrate to form a semiconductor wafer, forming a plurality of scribe lines, including a first scribe line, in the epitaxial layer, forming a mark in the first scribe line, inspecting the epitaxial layer for a crystal defect using crystal defect inspection equipment, which recognizes the first scribe line as being a second scribe line, forming a device element structure in the semiconductor wafer, dicing the semiconductor wafer into semiconductor chips along the scribe lines, and identifying, as a conforming product candidate, one of the semiconductor chips that is free of the crystal defect detected during the inspecting. A distance between an edge of the second scribe line and an edge of the mark, when the first and second scribe lines are aligned, is in a range from 10 μm to 25 μm.

A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.

A type, size, and location of a crystal defect of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected from a PL image by crystal defect inspection equipment. Detected crystal defects include a triangular polymorph stacking fault generated in the epitaxial layer during epitaxial growth and high-density BPDs extending from the stacking fault and present bundled between the stacking fault and a perfect crystal. Next, a chip region free of the triangular polymorph stacking fault and free of the high-density BPD in a specified area that is in the termination region and is located closer to a chip center than is a specified position is identified as a conforming product. A semiconductor chip set as a conforming product may contain high-density BPDs outside the specified area.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.