The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

A method of transfer printing. The method comprising: providing a precursor photonic device, comprising a substrate and a bonding region, wherein the precursor photonic device includes one or more alignment marks located in or adjacent to the bonding region; providing a transfer die, said transfer die including one or more alignment marks; aligning the one or more alignment marks of the precursor photonic device with the one or more alignment marks of the transfer die; and bonding at least a part of the transfer die to the bonding region.

A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

A method for forming a semiconductor structure includes receiving a first die having a first interconnect structure and a first bonding layer over the first interconnect structure, and a second die having a second interconnect structure and a second bonding layer over the second interconnect structure; forming a recess indenting into the first bonding layer; and forming a positioning member on the second bonding layer. The method further includes bonding the second die over the first die; and disposing the positioning member into the recess. The positioning member includes dielectric, is surrounded by the first bonding layer, and is isolated from the first interconnect structure and the second interconnect structure.

A semiconductor device, including a board, a semiconductor module disposed on a front surface of the board, and a case that includes (1) side wall portions that are disposed on the front surface of the board and that surround, with the board, a storage area including the semiconductor module, (2) a cover portion that is disposed on the side wall portions to cover the storage area, the cover portion having a terminal opening formed therein, and (3) a guiding projection portion formed on an inner surface of the cover portion, and protruding toward the storage area. The semiconductor device further includes sealing material with which the storage area is filled and which seals the semiconductor module. The guiding projection portion has a projecting end portion that is in contact with the sealing material.

An optical apparatus includes a folding mirror configured to direct first and second illumination lights on first and second alignment marks respectively and reflect first and second reflected lights reflected from the first and second alignment marks in different horizontal directions respectively, first and second lenses arranged respectively in optical paths of the first and second reflected lights reflected from the first and second reflective surfaces of the folding mirror, first and second reflection portions configured to reflect the first and second reflected lights passing through the first and second lenses respectively, and a beam splitter prism configured to divide an illumination light incident through a first surface into the first and second illumination lights and direct to the first and second reflection portions, and transmit the first and second reflected lights reflected by the first and second reflection portions through a second surface.

In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.

An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.