A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the plurality of transistors includes a gate all around structure.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

A sample mapping system includes a sample chuck including absolute reference marks, an imaging metrology tool to capture sets of alignment images at locations associated with sample marks on a sample on the sample chuck, and a controller. A particular set of alignment images at a particular location may include at least one alignment image associated with a particular sample mark and at least one alignment image associated with a particular portion of the absolute reference marks within a field of view of the imaging metrology tool visible through the sample. The controller may determine absolute coordinates of the sample marks based on the sets of alignment images. Determining the absolute coordinates of the particular sample mark may include determining the absolute coordinates of the particular sample mark based on a position of the particular sample mark relative to the particular portion of the absolute reference marks.

Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.