Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.

Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate.

The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

Provided is a semiconductor device capable of maintaining the flatness of a glass substrate and sufficiently protecting an end portion of the glass substrate. A semiconductor device according to one aspect of the present disclosure includes: a glass substrate including a first surface, a second surface opposite to the first surface, and a first side surface between the first surface and the second surface; wirings provided on the first and second surfaces; a first insulating film that covers the first surface; a second insulating film that covers the second surface; and a third insulating film that covers the first side surface, the third insulating film being continuous with at least one of the first and second insulating films.

The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier; forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.

A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

A method and apparatus for wafer bonding. The method includes that, a first position parameter of a first alignment mark on a first wafer is determined by using a optical beam; a second position parameter of a second alignment mark on a second wafer is determined with the optical beam, the optical beam has a property of transmitting through a wafer; a relative position between the first wafer and the second wafer is adjusted with the optical beam according to the first position parameter and the second position parameter until the relative position between the first alignment mark and the second alignment mark satisfies a predetermined bonding condition; and the first wafer is bonded to the second wafer.

A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

In a wiring member, an element connection portion, a plate connection portion, and an upper surface portion are at height positions different from one another. The element connection portion has a through hole, and the plate connection portion has a through hole and a chamfer. The upper surface portion which is not connected to another portion, has projections asymmetrically disposed on both side surfaces thereof. Owing to these features, the type, the orientation, and the front and the back of the wiring member can be easily distinguished. Accordingly, it is possible to prevent incorrect assembling of the wiring member in a semiconductor module.

An imprint apparatus includes a deforming mechanism for deforming a pattern region of a mold, and performs, after first processing for applying a first deformation amount, second processing for curing an imprint material in a state where the imprint material and the pattern region are in contact with each other and where a second deformation amount is given to the mold by the deforming mechanism to reduce an overlay error between each shot region and the pattern region. A magnitude relation between a driving force of the deforming mechanism required to set a deformation amount of the mold to the first deformation amount and a driving force of the deforming mechanism required to set the deformation amount of the mold to the second deformation amount varies depending on a magnitude of the driving force of the deforming mechanism for setting the deformation amount to the second deformation amount.